BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure

Claim 3

The method of claim 1, wherein said step (f) includes driving-in said first dopant implanted in step (c) to form a central emitter region to a depth having a range of about 0.20μ to about 0.30μ.

Claim 4

The method of claim 1, wherein said step (f) includes driving-in said like polarity dopant implanted in step (e) to a depth having a range of about 0.1μ to about 0.2μ.

Claim 5

The method of claim 1, wherein step (f) includes driving-in after step (c) and after step (e), and said driving-in after step (e) has a time duration less than ten percent of the duration of said driving-in after step (c).

Claim 6

The method of claim 1, wherein said step (f) includes a driving-in regime selected from the group consisting of driving-in immediately after step (c) for approximately 30 minutes at about 900° C., and driving-in immediately after step (e) for approximately 30 seconds at about 900° C.

Claim 7

The method of claim 1, wherein at least one of said step (f) includes an annealing process selected from the group consisting of low temperature furnace annealing and rapid thermal annealing.

Claim 8

The method of claim 1, wherein said step (b) includes forming said emitter window in an inverted "T" shape.

Claim 9

The method of claim 1, wherein at step (b) said cap layer portion extends a lateral distance of about 0.2μ to about 0.3μ.

Claim 10

The method of claim 1, wherein said forming step (b) includes etching said cap layer and said blocking layer.

Claim 11

The method of claim 1, wherein said forming step (b) includes the steps of reactive ion etching said cap layer and then undercutting said blocking layer to produce the cap layer extension.

Claim 12

The method of claim 10, wherein said step of undercutting includes wet etching said blocking layer.

Claim 13

The method of claim 1, wherein at step (a) said cap layer includes a material selected from the group consisting of photoresist, oxide and nitride.

Claim 14

The method of claim 1, wherein at step (a) said blocking layer includes a material selected from the group consisting of oxide, nitride and polysilicon.

Claim 15

The method of claim 1, wherein step (a) includes the step of doping said blocking layer.

Claim 16

The method of claim 1, wherein step (a) includes the step of forming said blocking layer to a thickness between about 2000 Å and about 4000 Å.

Claim 17

The method of claim 1, wherein step (a) includes the step of forming said cap layer to a thickness of about 500 Å to about 1,000 Å.

Claim 18

The method of claim 1, wherein step (a) includes the step of producing said cap layer by low pressure chemical vapor deposition.

Claim 19

The method of claim 1, wherein at step (c) said first dopant is implanted with a dosage level of about 3×10 15 /cm 2 .

Claim 20

The method of claim 1, wherein a step (e) said like polarity dopant is implanted with a dosage level of about 2×10 13 /cm 2 .

Claim 21

The method of claim 1, wherein step (c) is carried out with an implant energy less than about 50 kV.

Claim 22

The method of claim 1, wherein at step (c) said first dopant includes arsenic.

Claim 23

The method of claim 1, wherein said transistor is an NPN device, and said first polarity dopant includes arsenic.

Claim 24

A BiCMOS compatible method of fabricating, on a substrate that includes a collector region and a base region, a bipolar transistor with improved hot carrier characteristics and a MOS transistor, the method comprising the following steps: (a) forming above the base region and above a desired gate region a blocking layer and a cap layer overlying said blocking layer; (b) forming central emitter, source and drain windows in said layers; wherein said central emitter window is formed in said layers overlying a desired central emitter region such that said cap layer extends a desired lateral distance over said emitter window; wherein said source window and said drain window are formed in said layers overlying desired source and drain regions of the MOS transistor such that said cap layer extends a desired lateral distance over said source and drain windows; (c) implanting at a first dosage a first dopant through said central emitter window into said desired central emitter region, and through said source window and said drain window; (d) removing said cap layer; (e) implanting a dopant of like polarity to said first dopant through said central emitter window and through said source and drain windows at a dosage level that is at least a factor of ten lower than said first dosage level; and (f) after at least one of steps (c) and (e), driving-in said previously implanted dopant to form an emitter region, a source region and a drain region, each of said emitter, source and drain regions having a depth determined by said driving-in step; wherein said central emitter window determines said central emitter region's lateral extent and said cap layer portion extending over said central emitter window determines a lateral extent of a graded emitter region bounding said central emitter region of, said graded emitter region being lightly doped relative to said central emitter region; and wherein said cap layer portion extending over said source window determines a lateral extend of a graded source region bounding said source region of said MOS transistor, and said cap layer portion extending over said drain window determines a lateral extent of a graded drain region bounding said drain region of said MOS transistor, said graded source and drain regions being lightly doped relative to said source and drain regions respectively.

Claim 25

A BiCMOS compatible method of fabricating, on a substrate that includes a collector region and a base region, a bipolar transistor with improved hot carrier characteristics and a MOS transistor, the method comprising the following steps: (a) forming above the base region and above a desired gate region a blocking layer and a cap layer overlying said blocking layer; (b) forming central emitter, source and drain windows in said layers; wherein said central emitter window is formed in said layers overlying a desired central emitter region such that said cap layer extends a desired lateral distance over said emitter window; wherein said source window and said drain window are formed in said layers overlying desired source and drain regions of the MOS transistor such that said cap layer extends a desired lateral distance over said source and drain windows; (c) implanting at a first dosage a first dopant through said central emitter window into said desired central emitter region, and through said source window and said drain window; (d) removing said cap layer; (e) implanting a dopant of like polarity to said first dopant through said central emitter window and through said source and drain windows at a dosage level that is at least a factor of ten lower than said first dosage level; and (f) after at least one of steps (c) and (e), driving-in said previously implanted dopant to form an emitter region, a source region and a drain region, each of said emitter, source and drain regions having a depth determined by said driving-in step; wherein said central emitter window determines said central emitter region's lateral extent and said cap layer portion extending over said central emitter window determines a lateral extent of a graded emitter region bounding said central emitter region of, said graded emitter region being lightly doped relative to said central emitter region; and wherein said cap layer portion extending over said source window determines a lateral extend of a graded source region bounding said source region of said MOS transistor, and said cap layer portion extending over said drain window determines a lateral extent of a graded drain region bounding said drain region of said MOS transistor, said graded source and drain regions being lightly doped relative to said source and drain regions respectively.

Claim 26

The method of claim 23, wherein step (b) includes forming said emitter window in a shape approximating an inverted "T".

Claim 27

The method of claim 23, wherein step (b) includes forming said source and drain windows in a shape approximating an upright "T".

Claim 28

The method of claim 23, wherein said step (f) includes driving-in said first dopant implanted in step (c) to form a central emitter region, a source region and a drain region, each said central emitter, source and drain region having a depth in the range of about 0.20μ to about 0.30μ.

Claim 29

The method of claim 23, wherein said step (f) includes driving-in said like polarity dopant implanted in step (e) to a depth having a range of about 0.1μ to about 0.2μ.

Claim 30

The method of claim 23, wherein step (f) includes driving-in after step (c) and after step (e), and said driving-in after step (e) has a time duration less than ten percent of the duration of said driving-in after step (c).

Claim 31

The method of claim 23, wherein said step (f) includes a driving-in regime selected from the group consisting of driving-in immediately after step (c) for approximately 30 minutes at about 900° C., and driving-in immediately after step (e) for approximately 30 seconds at about 900° C.

Claim 32

The method of claim 23, wherein at least one of said step (f) includes an annealing process selected from the group consisting of low temperature furnace annealing and rapid thermal annealing.

Claim 33

The method of claim 23, wherein at step (b) a said cap layer portion extends a lateral distance of about 0.2μ to about 0.3μ.

Claim 34

The method of claim 23, wherein said forming step (b) includes etching said cap layer and said blocking layer.

Claim 35

The method of claim 23, wherein said forming step (b) includes the steps of reactive ion etching said cap layer and then undercutting said blocking layer to produce the cap layer extension.

Claim 36

The method of claim 33, wherein said step of undercutting includes wet etching said blocking layer.

Claim 37

The method of claim 23, wherein at step (a) said cap layer includes a material selected from the group consisting of photoresist, oxide and nitride.

Claim 38

The method of claim 23, wherein at step (a) said blocking layer includes polysilicon.

Claim 39

The method of claim 23, wherein step (a) includes the step of doping said blocking layer.

Claim 40

The method of claim 23, wherein step (a) includes the step of forming said blocking layer to a thickness between about 2000 Å and about 4000 Å.

Claim 41

The method of claim 23, wherein step (a) includes the step of forming said cap layer to a thickness of about 500 Å to about 1,000 Å.

Claim 42

The method of claim 23, wherein step (a) includes the step of producing said cap layer by low pressure chemical vapor deposition.

Claim 43

The method of claim 23, wherein at step (c) said first dopant is implanted with a dosage of about 3×10 15 /cm 2 .

Claim 44

The method of claim 23, wherein at step (e) said like polarity dopant is implanted with a dosage of about 2×10 13 /cm 2 .

Claim 45

The method of claim 23, wherein step (c) is carried out with an implant energy less than about 50 kV.

Claim 46

The method of claim 23, wherein at step (c) said first dopant includes arsenic.

Claim 47

The method of claim 23, wherein said transistor is an NPN device, and said first polarity dopant includes arsenic.