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Device for inserting information bits into a specific frame structure

Assignee: Alcatel CIT SA
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Filing: 1993-03-01
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Granted: 1994-02-15
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Expires: 2013-03-01
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Abstract

Abstract A device for inserting information bits into a specific frame structure essentially comprises an elastic memory whose capacity is designed to contain at each time defined by a reduced insertion bit rate D2/N a variable number of bits of words read in a buffer memory written at a reduced bit rate D1/N not yet inserted or not yet reinserted in the outgoing frames, this number varying according to justification commands generated previously, devices for selecting bits contained in said elastic memory for insertion or reinsertion in the outgoing frames, and devices for temporarily blocking the buffer memory read clock if the number of bits to store in the elastic memory exceeds a predetermined limit value.

Inventors

  • 👤 Philippe Regent

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:54
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076; H04J3/12

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 273 words
A device for inserting information bits into a specific frame structure at specific locations at least one of which may contain at least one justification opportunity bit, said device comprising: means for dividing the incoming digital bit stream with bit rate D1 into N bit streams with a reduced bit rate D1/N, a buffer memory into which are written at the bit rate D1/N and read at the bit rate D2/N successive words of n bits from said dividing mean, where D2/N denotes a reduced insertion bit rate at which said words are inserted in the outgoing frames, associated with justification control means adapted to compare the read and write bit rates of said buffer memory and generate a justification command, an elastic memory having a capacity determined to contain at each time defined by the reduced insertion bit rate D2/N a variable number of bits of words read in said buffer memory and not yet inserted or not yet reinserted into the outgoing frames, said variable number varying according to previously generated justification commands, means for selecting at each time defined by the reduced insertion bit rate D2/N, and according to previously generated justification commands, n bits contained in said elastic memory which are to be inserted or are to be reinserted at this time, means for providing a signal representing a present value of said variable number, and means responsive to said signal for temporarily blocking the clock for reading said buffer memory if the justification command generated at a given time is such that the number of bits to be stored in said elastic memory exceeds a predetermined limit value.
Claim 2
Independent Claim 273 words
A device for inserting information bits into a specific frame structure at specific locations at least one of which may contain at least one justification opportunity bit, said device comprising: means for dividing the incoming digital bit stream with bit rate D1 into N bit streams with a reduced bit rate D1/N, a buffer memory into which are written at the bit rate D1/N and read at the bit rate D2/N successive words of n bits from said dividing mean, where D2/N denotes a reduced insertion bit rate at which said words are inserted in the outgoing frames, associated with justification control means adapted to compare the read and write bit rates of said buffer memory and generate a justification command, an elastic memory having a capacity determined to contain at each time defined by the reduced insertion bit rate D2/N a variable number of bits of words read in said buffer memory and not yet inserted or not yet reinserted into the outgoing frames, said variable number varying according to previously generated justification commands, means for selecting at each time defined by the reduced insertion bit rate D2/N, and according to previously generated justification commands, n bits contained in said elastic memory which are to be inserted or are to be reinserted at this time, means for providing a signal representing a present value of said variable number, and means responsive to said signal for temporarily blocking the clock for reading said buffer memory if the justification command generated at a given time is such that the number of bits to be stored in said elastic memory exceeds a predetermined limit value.
Claim 3
Dependent Claim 21 words
Device according to claim 1, wherein said predetermined limit value for filling of said elastic memory is equal to 2n-1 bits.
Claim 4
Dependent Claim 63 words
Device according to claim 1, wherein said specific location likely to comprise at least one justification opportunity bit comprises also at least one stuff bit, and the number of bits stored in said elastic memory and the control of said selector means, at each time defined by the reduced insertion bit rate D2/N are conditioned also by the number of frames constructed previously.
Claim 5
Dependent Claim 33 words
Device according to claim 1, wherein said elastic memory comprises first and second registers each of n bits forming a shift register for n-bit words, the first receiving words from the buffer memory.
Claim 6
Dependent Claim 44 words
Device according to claim 4, wherein said selector means comprise a set of n selector units adapted to select m first bits from said first register and n-m last bits from said second register for all values of m between one and n inclusive.
Claim 7
Dependent Claim 79 words
Device according to claim 5, wherein said predetermined limit value for filling of said elastic memory is equal to 2n-1 bits and wherein the selector units are controlled by a counter with a capacity of n incremented at the reduced insertion bit rate for insertion of n-bit words likely to comprise a justification opportunity bit and comprising a stuff bit and the increment of which is adapted to assume one of two possible values according to the justification command.
Claim 8
Dependent Claim 7 words
Device according to claim 1, wherein N=n.

References Cited (Backward Citations)

DE3600795A1 Cited
US4920547A Cited
US4884268A Cited
EP0334357A2 Cited
US5030951A Cited
US5067126A Cited
US5091907A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-14 1997-08-16 1998-02-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-14 2001-08-16 2002-02-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-14 2005-08-16 2006-02-15 $7700.00 Window Closed / Lapsed

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