← Back to Patent Explorer
US5067126A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for mapping a digital signal carrier to another

Assignee: Telecommunications Res Labs
•
Filing: 1989-08-04
•
Granted: 1991-11-19
•
Expires: 2009-08-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy.

Inventors

  • 👤 Thomas E. Moore

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 18:20
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076; Y; Y10; Y10S; Y10S370/00; Y10S370/901; Y10S370/902; Y10S370/903; Y10S370/907

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 64 words
A process for the mapping of a first digital signal carrier carrying a first multiplexed digital signal to a second digital signal carrier comprising: demultiplexing the first digital signal to produce a second digital signal and to derive a gapped clock; writing the second digital signal to an elastic store using the gapped clock; and reading the second digital signal from the elastic store.
Claim 2
Dependent Claim 64 words
A process for the mapping of a first digital signal carrier carrying a first multiplexed digital signal to a second digital signal carrier comprising: demultiplexing the first digital signal to produce a second digital signal and to derive a gapped clock; writing the second digital signal to an elastic store using the gapped clock; and reading the second digital signal from the elastic store.
Claim 3
Dependent Claim 15 words
The process of claim 1 in which the second digital signal is a SONET signal.
Claim 4
Dependent Claim 79 words
Apparatus for the mapping of a first digital signal carrier carrying a first digital signal to a second digital signal carrier comprising: a demultiplexer for demultiplexing the first digital signal to produce a second digital signal; gapping means for gapping the first digital signal carrier to derive a gapped clock; writing means for writing the second digital signal to an elastic store using the gapped clock; and reading means for reading the second digital signal from the elastic store.
Claim 5
Dependent Claim 79 words
Apparatus for the mapping of a first digital signal carrier carrying a first digital signal to a second digital signal carrier comprising: a demultiplexer for demultiplexing the first digital signal to produce a second digital signal; gapping means for gapping the first digital signal carrier to derive a gapped clock; writing means for writing the second digital signal to an elastic store using the gapped clock; and reading means for reading the second digital signal from the elastic store.
Claim 6
Dependent Claim 69 words
Apparatus for mapping a DS-3 digital signal to a SONET signal, the apparatus comprising: a first demultiplexer for demultiplexing the DS-3 signal to generate a DS-2 signal and to generate a gapped DS-2 clock; a second demultiplexer to demultiplex the DS-2 signal to generate a DS-1 signal and to generate a gapped DS-1 clock; and bit stuffing means for bit stuffing the DS-1 signal to create a SONET signal.
Claim 7
Dependent Claim 69 words
Apparatus for mapping a DS-3 digital signal to a SONET signal, the apparatus comprising: a first demultiplexer for demultiplexing the DS-3 signal to generate a DS-2 signal and to generate a gapped DS-2 clock; a second demultiplexer to demultiplex the DS-2 signal to generate a DS-1 signal and to generate a gapped DS-1 clock; and bit stuffing means for bit stuffing the DS-1 signal to create a SONET signal.

References Cited (Backward Citations)

US4811340A Cited
US4791652A Cited
US4967405A Cited
US4928275A Cited
US4961188A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-11-18 1995-05-20 1995-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-11-18 1999-05-20 1999-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-11-18 2003-05-20 2003-11-19 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag