Non-volatile semiconductor memory device selectively skipping memory cells in programming

Claim 2

A non-volatile semiconductor memory device having an erasing mode, a programming mode and a read-out mode of operation, comprising: a) a memory cell array having a plurality of memory cells selectively entering erased state and write-in state for storing data bits, logic levels of each data bit being corresponding to said erased state and said write-in state, respectively; b) an addressing means operative to select at least one memory cell from said memory cell array for at least said programming mode and said read-out mode of operation; c) a read-out means operative to read out at least one data bit from said at least one memory cell; d) a controlling means storing at least one write-in data bit supplied from the outside thereof in said programming mode, and comparing said at least one write-in data bit with said at least one data bit to see whether or not the logic level of said at least one write-in data bit is inconsistent with the logic level of said at least one data bit, said controlling means being further operative to produce a prohibiting signal when said at least one write-in data bit is inconsistent with said at least one data bit, and e) a write-in means operative to write said at least one write-in data bit into said at least one memory cell in the absence of said prohibiting signal, said write-in means being prohibited from write-in of said at least one write-in data bit in the presence of said prohibiting signal.

Claim 3

A non-volatile semiconductor memory device having an erasing mode, a programming mode and a read-out mode of operation, comprising: a) a plurality of memory cells respectively storing data bits, and divisible into a plurality of memory blocks, each of said plurality of memory cells selectively entering erased state and write-in state which correspond to logic levels of each data bit; b) an addressing means operative to sequentially selects memory cells of one of said plurality of memory blocks; c) a read-out means operative to sequentially read out data bits from said memory cells of said one of said plurality of memory blocks; d) a controlling means sequentially storing write-in data bit supplied from the outside thereof in said programming mode, and sequentially comparing said write-in data bits with said data bits of said one of said plurality of memory blocks to see whether or not at lest one of said write-in data bits are inconsistent in logic level with a corresponding data bit of said data bits read out from said memory cells, said controlling means being further operative to produce a prohibiting signal when at least one write-in data bit is inconsistent with a corresponding data bit of said data bits, and e) a write-in means operative to write said write-in data bits into said memory cells of said one of said plurality of memory cell blocks in the absence of said prohibiting signal, said write-in means being prohibited from write-in of said write-in data bits to said one of said memory blocks in the presence of said prohibiting signal.

Claim 4

A non-volatile semiconductor memory device having an erasing mode, a programming mode and a read-out mode of operation, comprising: a) a plurality of memory cells respectively storing data bits, and divisible into a plurality of memory blocks, each of said plurality of memory cells selectively entering erased state and write-in state which correspond to logic levels of each data bit; b) an addressing means operative to sequentially selects memory cells of one of said plurality of memory blocks; c) a read-out means operative to sequentially read out data bits from said memory cells of said one of said plurality of memory blocks; d) a controlling means sequentially storing write-in data bit supplied from the outside thereof in said programming mode, and sequentially comparing said write-in data bits with said data bits of said one of said plurality of memory blocks to see whether or not at lest one of said write-in data bits are inconsistent in logic level with a corresponding data bit of said data bits read out from said memory cells, said controlling means being further operative to produce a prohibiting signal when at least one write-in data bit is inconsistent with a corresponding data bit of said data bits, and e) a write-in means operative to write said write-in data bits into said memory cells of said one of said plurality of memory cell blocks in the absence of said prohibiting signal, said write-in means being prohibited from write-in of said write-in data bits to said one of said memory blocks in the presence of said prohibiting signal.

Claim 5

A non-volatile semiconductor memory device as set forth in claim 2, in which said plurality of memory cells are implemented by floating gate type field effect transistors.

Claim 6

A non-volatile semiconductor memory device as set forth in claim 2, in which said addressing means comprises b-1) an address buffer unit coupled with a plurality of address pins, and operative to produce address predecoded signals, b-2) a row address decoder unit responsive to one of the address predecoded signals, and selectively driving word lines associated with the rows of said plurality of memory cells, and b-3) a column address decoder unit responsive to the other of said address predecoded signals for selecting one of a plurality sets of digit lines, said plurality sets of digit lines being respectively associated with said memory blocks.

Claim 7

A non-volatile semiconductor memory device as set forth in claim 4, in which said controlling means comprises d-1) a latch means associated with said plurality sets of digit lines, and storing said write-in data bits for said one of said plurality sets of digit lines selected by said column address decoder unit, and d-2) a comparator means operative to sequentially comparing said write-in data bits with said data bits of said one of said plurality of memory blocks to see whether or not at least one of said write-in data bits is inconsistent in logic level with a corresponding data bit of said data bits read out from said memory cells, said comparator means being further operative to produce said prohibiting signal.

Claim 8

A non-volatile semiconductor memory device as set forth in claim 5, in which said comparator means comprises d-2-1) a plurality of comparators associated with said plurality of memory blocks, respectively, and each comparing one of said write-in data bits with one of said data bits to see whether or not said one of said write-in data bit is inconsistent with said one of said data bits for producing an output signal indicative of inconsistency therebetween, said output signal being canceled with said reset signal, d-2-2) a signal generator supplied with said output signal of each of said comparator for producing said prohibiting signal.

Claim 9

A non-volatile semiconductor memory device as set forth in claim 2, in which said read-out means comprises c-1) a sense amplifier unit respectively associated with said plurality of memory blocks, and c-2) an input/output data buffer unit coupled between said sense amplifier unit and a plurality of input/output data pins.

Claim 10

A non-volatile semiconductor memory device as set forth in claim 2, in which said write-in means comprises e-1) said input/output data buffer unit, and e-2) a write-in circuit for selectively supplying an extremely high write-in voltage level to said one of said plurality sets of digit lines.

Claim 11

A non-volatile semiconductor memory device as set forth in claim 2, in which each of said plurality of memory blocks is further divisible into a plurality of memory sub-blocks, and in which said controlling means comprises d-1) a latch means having a plurality of latch circuit groups respectively associated with said plurality sets of digit lines, and responsive to latch signals for selectively storing said write-in data bits for said one of said plurality sets of digit lines, said latch signals being produced in association with said plurality of memory sub-blocks, respectively, d-2) a plurality of comparators respectively associated with said memory blocks, and each operative to sequentially comparing write-in data bits for the associated memory block with data bits read out from the associated memory block to see whether or not at least one of said write-in data bits is inconsistent in logic level with a corresponding data bit of said data bits read out from said associated memory block, said comparators being further operative to produce disable signals when finding inconsistency, and d-3) a decoder means coupled between said comparator means and said latch means, and responsive to said disable signals for producing said latch signals.