Capacitor for a BiCMOS device

Claim 3

The method according to claim 1 wherein the step of forming a first polysilicon terminal comprises: forming a first layer of polysilicon on at least the MOS region and on the first portion of the substrate; and selectively etching the first layer of polysilicon to form a gate electrode on the MOS transistor region and the first polysilicon terminal on the first portion of the substrate.

Claim 4

The method according to claim 1 wherein the step of oxide etching comprises selectively etching the oxide layer over the emitter window, the emitter window being substantially free of oxide.

Claim 5

The method according to claim 3 wherein the step of forming the second polysilicon terminal further comprises forming an emitter contact in the emitter window, the emitter contact formed by the steps of: forming a third polysilicon layer over the thin layer of polysilicon and in the emitter window; and selectively etching the third polysilicon layer to form the second polysilicon terminal over the first portion of the substrate and the emitter contact in the emitter window.

Claim 6

The method according to claim 1 wherein the thin layer of polysilicon is formed to a thickness of less than one-half the thickness of the first polysilicon terminal.

Claim 7

The method according to claim 5 wherein the thin layer of polysilicon is formed to a thickness of less than 1000 Angstroms.

Claim 8

A capacitor for a BiCMOS device on a substrate, the capacitor comprising: a first polysilicon layer on an insulative region over a first portion of the substrate; an oxide layer over the first polysilicon layer; a second polysilicon layer over the oxide layer; and a third polysilicon layer over the second polysilicon layer, wherein the second polysilicon is substantially thinner than the first and third polysilicon layer and further wherein the second and third polysilicon layers are electrically insulated form the first polysilicon layer.

Claim 9

A capacitor for a BiCMOS device on a substrate, the capacitor comprising: a first polysilicon layer on an insulative region over a first portion of the substrate; an oxide layer over the first polysilicon layer; a second polysilicon layer over the oxide layer; and a third polysilicon layer over the second polysilicon layer, wherein the second polysilicon is substantially thinner than the first and third polysilicon layer and further wherein the second and third polysilicon layers are electrically insulated form the first polysilicon layer.

Claim 10

A capacitor as in claim 7 wherein the second polysilicon layer is less than one-half the thickness of either the first or third polysilicon layers.

Claim 11

A capacitor as in claim 8 wherein the second polysilicon layer is less than 1000 Angstroms in thickness.

Claim 12

A capacitor for a BiCMOS device on a substrate, the substrate including a bipolar region and an MOS region, the capacitor formed by the steps of: forming a first layer of polysilicon on at least an insulative region over a first portion of the substrate laterally displaced from the bipolar and MOS regions; forming a layer of oxide over at least the bipolar region and the first portion of the substrate, the oxide layer covering the first layer of polysilicon; forming a second layer of polysilicon on the layer of oxide over at least the bipolar region and the first portion of the substrate; etching the thin polysilicon layer to form an exposed area of the layer of oxide over the bipolar transistor region; etching the oxide layer to form an emitter window over the bipolar region; dipping the exposed area to remove any native oxide off of the emitter window; and forming a third layer of polysilicon over the second layer of polysilicon just after the dipping step, wherein the second layer is substantially thinner than the first and third layers and wherein the second and third layers of polysilicon are electrically insulated form the first layer of polysilicon.

Claim 13

A capacitor for a BiCMOS device on a substrate, the substrate including a bipolar region and an MOS region, the capacitor formed by the steps of: forming a first layer of polysilicon on at least an insulative region over a first portion of the substrate laterally displaced from the bipolar and MOS regions; forming a layer of oxide over at least the bipolar region and the first portion of the substrate, the oxide layer covering the first layer of polysilicon; forming a second layer of polysilicon on the layer of oxide over at least the bipolar region and the first portion of the substrate; etching the thin polysilicon layer to form an exposed area of the layer of oxide over the bipolar transistor region; etching the oxide layer to form an emitter window over the bipolar region; dipping the exposed area to remove any native oxide off of the emitter window; and forming a third layer of polysilicon over the second layer of polysilicon just after the dipping step, wherein the second layer is substantially thinner than the first and third layers and wherein the second and third layers of polysilicon are electrically insulated form the first layer of polysilicon.

Claim 14

A capacitor according to claim 10 wherein the step of forming a first polysilicon layer further comprises: forming the first layer of polysilicon on at least the MOS region of the substrate; and selectively etching the first layer of polysilicon to form a gate electrode on the MOS region and a first capacitor terminal on the first portion of the substrate.

Claim 15

The capacitor according to claim 10 wherein the step of oxide etching comprises selectively etching the oxide layer over the emitter window, the emitter window being substantially free of oxide.

Claim 16

The capacitor according to claim 12 wherein the step of forming the third polysilicon layer further comprises forming an emitter contact in the emitter window, the emitter contact formed by the steps of: forming the third polysilicon layer in the emitter window; and selectively etching the third polysilicon layer to form a second capacitor terminal over the first portion of the substrate and the emitter contact in the emitter window.

Claim 17

A BICMOS device having at least a capacitor and a bipolar transistor formed in a substrate, wherein the capacitor comprises: a first polysilicon terminal on an insulative region over a first portion of the substrate; an oxide layer over the first polysilicon terminal; a thin polysilicon layer over the oxide layer; and a second polysilicon terminal over the thin polysilicon layer, the second polysilicon terminal being formed from a thick polysilicon layer deposited over the substrate and selectively etched, the thin polysilicon layer being substantially thinner than the first and second polysilicon terminals and the second polysilicon terminal being electrically insulated from the first polysilicon terminal; and wherein the bipolar transistor comprises: a base region formed in a second portion of the substrate laterally displaced from the first portion; an emitter formed in a third portion of the substrate adjacent the base region; and a polysilicon emitter contact overlying the emitter in electrical contact therewith, the emitter contact being formed from the thick polysilicon layer used to form the second polysilicon terminal of the capacitor.

Claim 18

A BICMOS device having at least a capacitor and a bipolar transistor formed in a substrate, wherein the capacitor comprises: a first polysilicon terminal on an insulative region over a first portion of the substrate; an oxide layer over the first polysilicon terminal; a thin polysilicon layer over the oxide layer; and a second polysilicon terminal over the thin polysilicon layer, the second polysilicon terminal being formed from a thick polysilicon layer deposited over the substrate and selectively etched, the thin polysilicon layer being substantially thinner than the first and second polysilicon terminals and the second polysilicon terminal being electrically insulated from the first polysilicon terminal; and wherein the bipolar transistor comprises: a base region formed in a second portion of the substrate laterally displaced from the first portion; an emitter formed in a third portion of the substrate adjacent the base region; and a polysilicon emitter contact overlying the emitter in electrical contact therewith, the emitter contact being formed from the thick polysilicon layer used to form the second polysilicon terminal of the capacitor.