US5286985A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface circuit operable to perform level shifting between a first type of device and a second type of device
Assignee: Texas Instruments Inc
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Filing: 1992-12-22
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Granted: 1994-02-15
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Expires: 2012-12-22
Abstract
Abstract Interface circuits for connecting gallium arsenide circuits with silicon circuits with the interface circuits using a mix of gallium arsenide and silicon devices. Preferred embodiments (200) connect gallium arsenide buffered FET logic circuits (202) with silicon CMOS circuits with a two branch interface circuit under CMOS supply voltages with a BFL logic branch (208-210) merged with a CMOS inverter branch (204-206).
Inventors
- 👤 Albert H. Taddiken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/02; H10D84/08
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
119 words
An interface circuit between first and second types of devices, said interface circuit operable to perform level shifting of first signals generated by said first type of device to second signals compatible with said second type of device, said interface comprising: (a) a first series path comprising at least two devices of a first type including two MESFETs in series either between a common bias supply and ground or between said common bias supply and a second bias supply; and (b) a second series path comprising, either a third MESFET of said first type or a p-channel MOSFET of said second type and an n-channel MOSFET of said second type in series between said common bias supply and ground.
Claim 2
Dependent Claim
119 words
An interface circuit between first and second types of devices, said interface circuit operable to perform level shifting of first signals generated by said first type of device to second signals compatible with said second type of device, said interface comprising: (a) a first series path comprising at least two devices of a first type including two MESFETs in series either between a common bias supply and ground or between said common bias supply and a second bias supply; and (b) a second series path comprising, either a third MESFET of said first type or a p-channel MOSFET of said second type and an n-channel MOSFET of said second type in series between said common bias supply and ground.
Claim 3
Dependent Claim
24 words
The interface circuit of claim 1, wherein: (a) said MOSFETs are formed principally of silicon; and (b) said MESFETs are formed principally of GaAs.
Claim 4
Dependent Claim
54 words
The interface circuit of claim 1, wherein: (a) said first series path includes two GaAs MESFETs in series between said common bias supply and a second bias supply; and (b) said second series path type includes a silicon n-channel MOSFET in series with said GaAs third MESFET between said common bias supply and ground.
References Cited (Backward Citations)
US4554569A
Cited
US4507846A
Cited
US4654548A
Cited
US4732870A
Cited
US4710478A
Cited
US4774205A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |