Patent US5286678A successfully refreshed from Google Patents.
US5286678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single step salicidation process
Assignee: Intel Corp
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Filing: 1992-09-28
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Granted: 1994-02-15
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Expires: 2012-09-28
Abstract
Abstract The present invention generally involves the fabrication of semiconductor devices so as to reduce the active region to interconnect interface resistivity. Fabrication begins by forming active regions on a semiconductor device. Next, a titanium metal of approximately 900 (Aangstroem) thickness is deposited on the semiconductor device. The semiconductor device is then annealed in a single step to form the interconnects.
Inventors
- 👤 Rajiv Rastogi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:58
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
84 words
An improved method of fabricating a semiconductor device with mean sheet resistivity less than 1 ohm per square, said improved method comprising: a) forming active regions on said semiconductor device; b) depositing a titanium metal on said active regions; c) annealing said semiconductor device in a single step at a temperature within a range of 630° C.-650° C. and for approximately 90 seconds while maintaining nitrogen gas flow to produce an entirely C54 phase of tisalicide; and d) forming interconnects on said semiconductor device.
Claim 2
Dependent Claim
84 words
An improved method of fabricating a semiconductor device with mean sheet resistivity less than 1 ohm per square, said improved method comprising: a) forming active regions on said semiconductor device; b) depositing a titanium metal on said active regions; c) annealing said semiconductor device in a single step at a temperature within a range of 630° C.-650° C. and for approximately 90 seconds while maintaining nitrogen gas flow to produce an entirely C54 phase of tisalicide; and d) forming interconnects on said semiconductor device.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein said temperature is ramped at a rate of 90° C. per second.
Claim 4
Dependent Claim
109 words
An improved method of fabricating a semiconductor device, said improved method comprising: a) forming active regions on said semiconductor device; b) forming a gate on said semiconductor device; c) forming oxide spacers between said active regions and said gate; d) depositing a layer of titanium on said semiconductor device, the titanium layer having a thickness of approximately 900 Å; e) implanting silicon in said semiconductor device; f) annealing said semiconductor device in a single step at a temperature within a range of 630° C.-650° C. for approximately 90 seconds while maintaining a nitrogen gas flow to produce an entirely C54 phase of tisalicide; and g) etching said semiconductor device.
Claim 5
Dependent Claim
109 words
An improved method of fabricating a semiconductor device, said improved method comprising: a) forming active regions on said semiconductor device; b) forming a gate on said semiconductor device; c) forming oxide spacers between said active regions and said gate; d) depositing a layer of titanium on said semiconductor device, the titanium layer having a thickness of approximately 900 Å; e) implanting silicon in said semiconductor device; f) annealing said semiconductor device in a single step at a temperature within a range of 630° C.-650° C. for approximately 90 seconds while maintaining a nitrogen gas flow to produce an entirely C54 phase of tisalicide; and g) etching said semiconductor device.
Claim 6
Dependent Claim
19 words
The method of claim 3 wherein said annealing is performed with a ramp rate of 90° C. per second.
Claim 7
Dependent Claim
21 words
The method of claim 4 wherein during said annealing said nitrogen gas flow has a rate of 2 liters per minute.
Claim 8
Dependent Claim
84 words
An improved method of reducing the mean sheet resistance of a device to less than 1 ohm per square on a semiconductor device before forming interconnects, said improved method comprising: a) depositing on said device a titanium metal, the titanium metal having a thickness of 900 Å; and b) annealing said titanium metal in a single step at a temperature within a range of 630° C.-650° C. for 90 seconds while maintaining a nitrogen gas flow to produce an entirely C54 phase of tisalicide.
Claim 9
Dependent Claim
84 words
An improved method of reducing the mean sheet resistance of a device to less than 1 ohm per square on a semiconductor device before forming interconnects, said improved method comprising: a) depositing on said device a titanium metal, the titanium metal having a thickness of 900 Å; and b) annealing said titanium metal in a single step at a temperature within a range of 630° C.-650° C. for 90 seconds while maintaining a nitrogen gas flow to produce an entirely C54 phase of tisalicide.
Claim 10
Dependent Claim
22 words
The method of claim 6 wherein said annealing in step (b) is performed with a ramp rate of 90° C. per second.
Claim 11
Dependent Claim
18 words
The method of claim 7 wherein said nitrogen gas flow has a rate of 2 liters per minute.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |