US5285408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for providing a faster ones voltage level restore operation in a dram
Assignee: Micron Technology Inc
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Filing: 1992-09-15
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Granted: 1994-02-08
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Expires: 2012-09-15
Abstract
Abstract There is a DRAM which provides for a faster non-accessed memory cell ones voltage level refresh or restore process. Specifically, the DRAM does not shut down a digit line's voltage pull-up circuitry (PSA) during a write operation. By leaving on the PSA, the digit lines being pulled to a ones voltage level will continue to be pulled up during the write operation. Thus, a non-accessed digit line will reach the ones voltage level in a shorter time than if the PSA were turned off during the write operation.
Inventors
- 👤 Michael W. Starkweather
- 👤 Paul S. Zagar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/4091
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
96 words
A method of operation for a DRAM device, comprising: providing a digit line voltage pull-up amplifying circuitry (PSA 20); providing a supply voltage; connecting the pull-up circuitry (20) to the supply voltage by at least a first (34) and second (36) current limiting circuit, said first circuit providing more current to the pull-up circuitry than the second circuit; maintaining current to the pull-up circuitry (20) during a read operation through the first and second current limiting circuits; maintaining current to the pull-up circuitry (20) during a write operation exclusively through the second current limiting circuit (36);
Claim 2
Independent Claim
96 words
A method of operation for a DRAM device, comprising: providing a digit line voltage pull-up amplifying circuitry (PSA 20); providing a supply voltage; connecting the pull-up circuitry (20) to the supply voltage by at least a first (34) and second (36) current limiting circuit, said first circuit providing more current to the pull-up circuitry than the second circuit; maintaining current to the pull-up circuitry (20) during a read operation through the first and second current limiting circuits; maintaining current to the pull-up circuitry (20) during a write operation exclusively through the second current limiting circuit (36);
Claim 3
Dependent Claim
141 words
A DRAM, comprising: pull-up sense amplifier (20); a supply voltage (Vcc); a first circuit line, connecting the supply voltage to the pull-up sense amplifier; and a second circuit line, connecting the supply voltage to the pull-up sense amplifier. first current limiting means (34), connected to said first circuit line, for limiting current going to the pull-up sense amplifier to a second current level; second current limiting means (36), connected to said second circuit line, for limiting the current going to the pull-up sense amplifier to a second current level lower than the first current level; the first current limiting means is a transistor that is turned on during a read operation of a DRAM and turned off during a write operation; and the second current limiting means is a transistor that is always left on during all operations of the DRAM.
Claim 4
Dependent Claim
141 words
A DRAM, comprising: pull-up sense amplifier (20); a supply voltage (Vcc); a first circuit line, connecting the supply voltage to the pull-up sense amplifier; and a second circuit line, connecting the supply voltage to the pull-up sense amplifier. first current limiting means (34), connected to said first circuit line, for limiting current going to the pull-up sense amplifier to a second current level; second current limiting means (36), connected to said second circuit line, for limiting the current going to the pull-up sense amplifier to a second current level lower than the first current level; the first current limiting means is a transistor that is turned on during a read operation of a DRAM and turned off during a write operation; and the second current limiting means is a transistor that is always left on during all operations of the DRAM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |