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US5283461A Expired / Lapsed US ⏱️ 0.0 years remaining

Trench conductor and crossunder architecture

Assignee: Intersil Corp
•
Filing: 1992-07-17
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Granted: 1994-02-01
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Expires: 2012-07-17
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Abstract

Abstract The trench pattern of a dielectrically isolated island architecture is filled with doped polysilicon and used as an interconnect structure for circuit devices that are supported within the islands, thereby decreasing the amount of topside interconnect and reducing the potential for parasitics beneath tracks of surface metal. The trench pattern may serve as a voltage distribution network or provide crossunders beneath surface tracks. In addition, at least one of the islands may contain one or more auxiliary poly-filled trench regions to perform the crossunder function. Such an auxiliary trench region may be also provided in an island that contains a circuit device. Manufacture of the conductor-filled trench structure may be facilitated by depositing polysilicon over a dielectrically coated trench grid structure and then planarizing the polysilicon to the surface of the oxide dielectric. The exposed polysilicon is doped and then oxidized to seal the dopant, which forms a thin oxide layer on the poly. The oxide dielectric for the trench can then be selectively patterned to form a mask to be for the initial doping of the islands.

Inventors

  • 👤 James D. Beasom

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 22:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/432; H10W20/20; H10W20/44; H10W20/4451; H10W72/00; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/15

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 147 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; electrically conductive material formed in said trench pattern and said auxiliary trench region; a first conductive layer overlying dielectric material atop the surface of said auxiliary trench region between first and second locations of electrically conductive material in said auxiliary trench region; and respective electrical connections between second and third conductive layers overlying said dielectric material and said first and second locations of electrically conductive material in said auxiliary trench region.
Claim 2
Dependent Claim 147 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; electrically conductive material formed in said trench pattern and said auxiliary trench region; a first conductive layer overlying dielectric material atop the surface of said auxiliary trench region between first and second locations of electrically conductive material in said auxiliary trench region; and respective electrical connections between second and third conductive layers overlying said dielectric material and said first and second locations of electrically conductive material in said auxiliary trench region.
Claim 3
Dependent Claim 19 words
A semiconductor structure according to claim 1, wherein said auxiliary trench region is formed in an electrically isolated island.
Claim 4
Dependent Claim 29 words
A semiconductor structure according to claim 2, further including at least one semiconductor device region formed in the electrically isolated island in which said auxiliary trench region is formed.
Claim 5
Dependent Claim 24 words
A semiconductor structure according to claim 1, wherein a plurality of auxiliary trench regions are formed in said selected portion of said semiconductor layer.
Claim 6
Dependent Claim 129 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and electrically conductive material formed in said trench pattern and said auxiliary trench region; and wherein said trench pattern and said auxiliary trench region are formed in a semiconductor layer that is dielectrically isolated from an underlying substrate, so that said semiconductor layer is subdivided into a plurality of spaced-apart, dielectrically isolated islands.
Claim 7
Dependent Claim 129 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and electrically conductive material formed in said trench pattern and said auxiliary trench region; and wherein said trench pattern and said auxiliary trench region are formed in a semiconductor layer that is dielectrically isolated from an underlying substrate, so that said semiconductor layer is subdivided into a plurality of spaced-apart, dielectrically isolated islands.
Claim 8
Dependent Claim 105 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and electrically conductive material formed in said trench pattern and said auxiliary trench region; and wherein a plurality of auxiliary trench regions are formed in an electrically isolated island.
Claim 9
Dependent Claim 105 words
A semiconductor structure comprising: a trench pattern formed in a semiconductor layer that is electrically isolated from an underlying substrate, said trench pattern subdividing said semiconductor layer into a plurality of spaced-apart, electrically isolated islands; an auxiliary trench region formed in a selected portion of said semiconductor layer spaced apart from said trench pattern; dielectric material formed on top surfaces of said semiconductor layer, and upon sidewalls of said trench pattern and said auxiliary trench region; and electrically conductive material formed in said trench pattern and said auxiliary trench region; and wherein a plurality of auxiliary trench regions are formed in an electrically isolated island.

References Cited (Backward Citations)

US4503451A Cited
EP0228320A1 Cited
US4953125A Cited
US4977439A Cited
EP0307844A2 Cited
US4939567A Cited
US4920389A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-01-31 1997-08-02 1998-02-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-01-31 2001-08-02 2002-02-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-01-31 2005-08-02 2006-02-01 $7700.00 Window Closed / Lapsed

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