Patent US5283204A successfully refreshed from Google Patents.
US5283204A
Expired / Lapsed
US
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Method of forming passivation oxidation for improving cell leakage and cell area
Assignee: Micron Technology Inc
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Filing: 1992-04-15
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Granted: 1994-02-01
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Expires: 2012-04-15
Abstract
Abstract The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. Fabrication methods are disclosed that, when used with existing capacitor fabrication processes, will reduce cell leakage and allow for increased capacitance. The present invention corrects any severed storage node poly that may have resulted from a misalignment of a masking pattern used for defining future buried contacts by placing passivation oxidation over the existing wafer surface which, in effect, seals off the severed storage node poly form the capacitor's top cell plate poly. The passivation oxidation prevents cell plate to plate leakage while protecting the severed storage node poly from subsequent deposition of conductive layers.
Inventors
- 👤 Howard E. Rhodes
- 👤 Tyler A. Lowrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:02
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
195 words
A process for isolating first and second conductive plates of a storage capacitor fabricated on a starting substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the starting substrate and forming insulative spacers on walls of said pair of parallel conductive access lines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate, said oxidation insulates said severed portions of said first conductive plate.
Claim 2
Dependent Claim
195 words
A process for isolating first and second conductive plates of a storage capacitor fabricated on a starting substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the starting substrate and forming insulative spacers on walls of said pair of parallel conductive access lines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate, said oxidation insulates said severed portions of said first conductive plate.
Claim 3
Dependent Claim
16 words
A process as recited in claim 1, wherein said oxidizing step is a wet oxidation step.
Claim 4
Dependent Claim
16 words
A process as recited in claim 1, wherein said oxidizing step is a dry oxidation step.
Claim 5
Dependent Claim
21 words
A process as recited in claim 1, wherein said annealing step is performed at a temperature range of approximately 700°-900° C.
Claim 6
Dependent Claim
20 words
A process as recited in claim 1, wherein said annealing step is performed at a temperature of approximately 800° C.
Claim 7
Dependent Claim
17 words
A process as recited in claim 1, wherein said first and second conductive plates are doped polysilicon.
Claim 8
Dependent Claim
15 words
A process as recited in claim 1, wherein the storage capacitor comprises a stacked capacitor.
Claim 9
Dependent Claim
15 words
A process as recited in claim 1, wherein said starting substrate is a silicon substrate.
Claim 10
Dependent Claim
14 words
A process as recited in claim 1, wherein the mask comprises a photoresist layer.
Claim 11
Dependent Claim
20 words
A process as recited in claim 1, wherein said parallel conductive access lines are wordlines in dynamic random access memory.
Claim 12
Dependent Claim
195 words
A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed silicon substrate, said oxidation insulates said severed portions of said first conductive plate.
Claim 13
Dependent Claim
195 words
A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed silicon substrate, said oxidation insulates said severed portions of said first conductive plate.
Claim 14
Dependent Claim
16 words
A process as recited in claim 11, wherein said oxidizing step is a wet oxidation step.
Claim 15
Dependent Claim
15 words
A process as recited in claim 11, wherein said oxidizing is a dry oxidation step.
Claim 16
Dependent Claim
21 words
A process as recited in claim 11, wherein said annealing step is performed at a temperature range of approximately 700°-900° C.
Claim 17
Dependent Claim
20 words
A process as recited in claim 11, wherein said annealing step is performed at a temperature of approximately 800° C.
Claim 18
Dependent Claim
17 words
A process as recited in claim 11, wherein said first and second conductive plates are doped polysilicon.
Claim 19
Dependent Claim
15 words
A process as recited in claim 11, wherein the storage capacitor comprises a stacked capacitor.
Claim 20
Dependent Claim
14 words
A process as recited in claim 11, wherein the mask comprises a photoresist layer.
Claim 21
Dependent Claim
182 words
A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing said surface during an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate.
Claim 22
Dependent Claim
182 words
A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of: a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor's second conductive plate; b) removing said second conductive plate's exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate's exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening; c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines; d) removing said mask; e) introducing conductive impurities into said exposed starting substrate; f) oxidizing said surface during an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate.
Claim 23
Dependent Claim
16 words
A process as recited in claim 19, wherein said oxidizing step is a wet oxidation step.
Claim 24
Dependent Claim
16 words
A process as recited in claim 19, wherein said oxidizing step is a dry oxidation step.
Claim 25
Dependent Claim
21 words
A process as recited in claim 19, wherein said annealing step is performed at a temperature range of approximately 700°-900° C.
Claim 26
Dependent Claim
20 words
A process as recited in claim 19, wherein said annealing step is performed at a temperature of approximately 800° C.
Claim 27
Dependent Claim
17 words
A process as recited in claim 19, wherein said first and second conductive plates are doped polysilicon.
Claim 28
Dependent Claim
15 words
A process as recited in claim 19, wherein the storage capacitor comprises a stacked capacitor.
Claim 29
Dependent Claim
14 words
A process as recited in claim 19, wherein the mask comprises a photoresist layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |