Patent US4415962A successfully refreshed from Google Patents.
Patent FR2490084A1 successfully refreshed from Google Patents.
US5282210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time-division-multiplexed data transmission system
Assignee: International Business Machines Corp
•
Filing: 1992-06-01
•
Granted: 1994-01-25
•
Expires: 2012-06-01
Abstract
Abstract A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.
Inventors
- 👤 Timothy J. Slegel
- 👤 Charlotte A. Reed
- 👤 Kirk D. Lamb
- 👤 Donald H. Friedberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:10
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
209 words
A multiplexer system comprising: a first latch for a first source of data signals; a second latch for a second source of data signals; means including a clocking signal having a clocking cycle establishing a cycle time for providing a first clocking signal at a given phase and frequency to said first and second latches to provide clocked outputs; a multiplexer for alternately coupling the clocked outputs from said first and second latches at first and second terminals respectively in response to a select control signal; and means for providing said select control signal at twice the clocking rate, said means for providing said select control signals including a first inverter coupled to a third latch with the output of the third latch coupled back to the input of said first inverter, a second inverter coupled to a fourth latch with the output of the fourth latch coupled back to the input of the second inverter, and an XOR gate responsive to the outputs from said third and fourth latches to provide said select control signal, said third latch output clocked out by said first clocking signals and said fourth latch clocked out by said clocking signal delayed approximately one-half of said clocking cycle time of the clocking cycle.
Claim 2
Dependent Claim
209 words
A multiplexer system comprising: a first latch for a first source of data signals; a second latch for a second source of data signals; means including a clocking signal having a clocking cycle establishing a cycle time for providing a first clocking signal at a given phase and frequency to said first and second latches to provide clocked outputs; a multiplexer for alternately coupling the clocked outputs from said first and second latches at first and second terminals respectively in response to a select control signal; and means for providing said select control signal at twice the clocking rate, said means for providing said select control signals including a first inverter coupled to a third latch with the output of the third latch coupled back to the input of said first inverter, a second inverter coupled to a fourth latch with the output of the fourth latch coupled back to the input of the second inverter, and an XOR gate responsive to the outputs from said third and fourth latches to provide said select control signal, said third latch output clocked out by said first clocking signals and said fourth latch clocked out by said clocking signal delayed approximately one-half of said clocking cycle time of the clocking cycle.
Claim 3
Dependent Claim
120 words
The combination claimed in claim 1 including a single coupling means coupled to said multiplexer for sending said multiplexed data signals to a receiving means, where delays over said coupling means is less than one-half the cycle time and said receiving means includes fifth and sixth latches connected in series to said coupling means, with said fifth latch coupled to said coupling means clocking data from said first source to said sixth latch using said delayed clocking signal and a seventh latch coupled to said coupling means clocked out by said first clocking signal, whereby a signal from a first data source is clocked into said sixth latch when said multiplexer couples a second data source into said seventh latch.
Claim 4
Dependent Claim
128 words
The combination claimed in claim 1 including a single coupling means coupled to said multiplexer for sending said multiplexed data signals to a receiving means where delays over said coupling means is greater than a half of the clocking signal cycle time and wherein said receiving means includes fifth and sixth latches connected in series to said coupling means, with said fifth latch coupled to said coupling means clocking data from said first source to said sixth latch by said first clocking signal and said receiving means including seventh and eight latches connected in series to said coupling means, and wherein said seventh data latch is clocked at said delayed clocking signal to couple second source data signals to said eight latch at a skewed clock cycle time.
Claim 5
Dependent Claim
46 words
The combination of claim 1 wherein said means for providing said select control signals is selectable between the clocking rate and twice the clocking rate by providing gate means between said second inverter and said fourth latch for providing, only when enabled, said delayed clocking signal.
Claim 6
Dependent Claim
56 words
The combination of claim 1 further including two-way select means between said first inverter and said third latch for in a first state coupling said inverter output to said third latch and in a second state providing a source select signal to said multiplexer and providing a feedback signal from said multiplexer to said first inverter.
References Cited (Backward Citations)
US3665405A
Cited
US3995120A
Cited
US4010385A
Cited
US4486880A
Cited
US4593390A
Cited
US4789984A
Cited
US4791628A
Cited
US4965797A
Cited
US4926423A
Cited
US5111455A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |