US4486880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output multiplexer having one gate delay
Assignee: Semiconductor Components Industries LLC
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Filing: 1982-12-09
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Granted: 1984-12-04
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Expires: 2002-12-09
Abstract
Abstract A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.
Inventors
- 👤 Philip A. Jeffery
- 👤 L. J. Reed
- 👤 Harold L. Spangler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:54
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/002; H03K17/005; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
156 words
A multiplexer having a plurality of input conductors each responsive to an input having a first and second state and a plurality of select conductors each responsive to a select signal, for providing an output, comprising: a select circuit comprising a plurality of gates, each of said input conductors coupled to at least two of said gates, each of said gates having a first gate output having a first and second state and a second gate output having a first and second state, each of said gates comprising differentially coupled transistors, each of said transistors having a collector, each of said collectors providing one of said first and second gate outputs, said collectors dotted with collectors of another one of said transistors so as to provide a plurality of select outputs; and a multiplexer gate coupled to said plurality of input conductors and said select circuit and responsive to said select outputs for determining said output.
Claim 2
Dependent Claim
156 words
A multiplexer having a plurality of input conductors each responsive to an input having a first and second state and a plurality of select conductors each responsive to a select signal, for providing an output, comprising: a select circuit comprising a plurality of gates, each of said input conductors coupled to at least two of said gates, each of said gates having a first gate output having a first and second state and a second gate output having a first and second state, each of said gates comprising differentially coupled transistors, each of said transistors having a collector, each of said collectors providing one of said first and second gate outputs, said collectors dotted with collectors of another one of said transistors so as to provide a plurality of select outputs; and a multiplexer gate coupled to said plurality of input conductors and said select circuit and responsive to said select outputs for determining said output.
Claim 3
Dependent Claim
230 words
A multiplexer having four input conductors, each responsive to an input, and two select conductors, each responsive to a select signal, for providing an output, comprising: a select circuit comprising: a first gate coupled to a first of said select conductors for providing a first gate signal and a first gate inverse signal; a second gate coupled to said first of said select conductors for providing a second gate signal and a second gate inverse signal; a third gate coupled to a second of said select conductors for providing a third gate signal and a third gate inverse signal; and a fourth gate coupled to said second of said select conductors for providing a fourth gate signal and a fourth gate inverse signal, said first gate inverse signal being combined with said third gate signal to provide a first select output, said first gate signal being combined with said third gate inverse signal to provide a second select output, said second gate signal being combined with said fourth gate signal to provide a third select output, said second gate inverse signal being combined with said fourth gate inverse signal to provide a fourth select output; and a multiplexer gate coupled to said four input conductors and said select circuit and responsive to said first through fourth select outputs for providing said output, said output having a first and second state.
Claim 4
Dependent Claim
230 words
A multiplexer having four input conductors, each responsive to an input, and two select conductors, each responsive to a select signal, for providing an output, comprising: a select circuit comprising: a first gate coupled to a first of said select conductors for providing a first gate signal and a first gate inverse signal; a second gate coupled to said first of said select conductors for providing a second gate signal and a second gate inverse signal; a third gate coupled to a second of said select conductors for providing a third gate signal and a third gate inverse signal; and a fourth gate coupled to said second of said select conductors for providing a fourth gate signal and a fourth gate inverse signal, said first gate inverse signal being combined with said third gate signal to provide a first select output, said first gate signal being combined with said third gate inverse signal to provide a second select output, said second gate signal being combined with said fourth gate signal to provide a third select output, said second gate inverse signal being combined with said fourth gate inverse signal to provide a fourth select output; and a multiplexer gate coupled to said four input conductors and said select circuit and responsive to said first through fourth select outputs for providing said output, said output having a first and second state.
Claim 5
Dependent Claim
115 words
The multiplexer according to claim 2 wherein said first, second, third, and fourth gates each comprise a first and second differentially connected transistor, a collector of said first transistor of said first gate being coupled to a collector of said first transistor of said second gate, a collector of said second transistor of said first gate being coupled to a collector of said second transistor of said second gate, a collector of said first transistor of said third gate being coupled to a collector of said first transistor of said fourth gate, a collector of said second transistor of said third gate being coupled to a collector of said second transistor of said fourth gate.
Claim 6
Dependent Claim
92 words
The multiplexer according to claim 2 wherein said multiplexer gate comprises: a fifth gate coupled to said first gate and a first of said four input conductors; a sixth gate coupled to said second gate and a second of said four input conductors; a seventh gate coupled to said third gate and a third of said four input conductors; an eighth gate coupled to said fourth gate and a fourth of said four input conductors; and a ninth gate coupled to said fifth, sixth, seventh, and eighth gate for providing said output.
Claim 7
Dependent Claim
27 words
The multiplexer according to claim 4 further comprising an enabling circuit responsive to an enable signal, said enabling circuit diverting current from said multiplexer gate when enabled.
References Cited (Backward Citations)
US3838296A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-04 | 1988-06-04 | 1988-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-04 | 1992-06-04 | 1992-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-04 | 1996-06-04 | 1996-12-04 | $7700.00 | Window Closed / Lapsed |