Serial access memory comprising disconnecting circuit between serial bus lines and preamplifier

Claim 2

A semiconductor memory device comprising: a plurality of memory cell columns; a plurality of bit line pairs, each connected to a corresponding one of said plurality of memory cell columns; a signal transmission line pair coupled to said plurality of bit line pairs for transmitting a data signal applied from said plurality of bit line pairs; equalize means connected to said signal transmission line pair for equalizing said signal transmission line pair; amplifying means, responsive an activation signal, for amplifying the data signal transmitted via said signal transmission line pair, said activation signal being generated in response to an externally applied clock signal and having a first level activating an amplifying operation and a second level deactivating said amplifying operation; and disconnecting means for electrically disconnecting said signal transmission line pair from said amplifying means after said amplifying means receives said activation signal at said first level and before said activation signal changes to said second level; wherein said equalize means commences equalizing operation of said signal transmission line pair after said disconnecting means electrically disconnects said transmission line pair from said amplifying means and before said activation signal changes to said second level.

Claim 3

The semiconductor memory device according to claim 1, wherein said equalize means is responsive to the first level of said activation signal to commence an equalizing operation after a predetermined time length has elapsed since activating said amplifying operation by said amplifying means in response to said the first level of said activation signal.

Claim 4

The semiconductor memory device according to claim 2, further comprising: disconnection control signal generating means responsive to said activation signal for generating a disconnection control signal to control said disconnecting means, said disconnecting means being operated in response to the disconnection control signal generated from said disconnection control signal generating means.

Claim 5

The semiconductor memory device according to claim 3, wherein said disconnection control signal generating means comprises rising edge delay means for receiving said activation signal at said first level, and for delaying the rising edge of said activation signal by said predetermined time length to provide the delayed signal as said disconnection control signal, said disconnecting means comprises switching means connected between said signal transmission line pair and said amplifying means, operating in response to the disconnection control signal provided from said rising edge delay means.

Claim 6

The semiconductor memory device according to claim 1, further comprising charge holding means connected to an input node of said amplifying means for holding a charge corresponding to said data signal transmitted via said signal transmission line pair.

Claim 7

The semiconductor memory device according to claim 5, wherein said charge holding means comprises capacitor means connected between said input node of said amplifying means and a predetermined potential.

Claim 8

The semiconductor memory device according to claim 1, said semiconductor memory device comprising a serial access memory device, said externally applied clock signal comprising a serial out clock signal.

Claim 9

The semiconductor memory device according to claim 1, wherein said amplifying means comprises a current mirror type amplifier operated in response to the activation signal.

Claim 10

The semiconductor memory device according to claim 8, wherein said amplifying means further comprises a cross coupled type amplifier formed by two NMOS transistors, said cross coupled type amplifier is operated in response to the activation signal.

Claim 11

A serial access memory device responsive to an externally applied serial out clock signal for providing in series a stored data signal, comprising: a plurality of memory cell columns, a plurality of bit line pairs, each connected to a corresponding one of said plurality of memory cell columns, a plurality of signal holding means, each connected to a corresponding one of said plurality of bit line pairs, for holding a data signal read out from said corresponding one memory cell column, a signal transmission line pair for transmitting a data signal provided from said plurality of signal holding means, a plurality of serial transfer means, each connected between said plurality of signal holding means and said signal transmission line pair, for transferring a data signal held in a corresponding one of said plurality of signal holding means to said signal transmission line pair, serial selecting means responsive to the serial out clock signal for selecting in series said plurality of serial transfer means, said plurality of serial transfer means responsive to said serial selecting means for transferring in series a data signal held by said plurality of signal holding means to said signal transmission line pair, equalize means connected to said signal transmission line pair for equalizing said signal transmission line pair, amplifying means responsive to the serial out clock signal for amplifying said data signal transmitted via said signal transmission line pair, and disconnecting means for electrically disconnecting said signal transmission line pair and said amplifying means after said amplifying means commences amplifying operation, said equalized means commencing equalized operation of said signal transmission line pair after said disconnecting means is operated.

Claim 12

A serial access memory device responsive to an externally applied serial out clock signal for providing in series a stored data signal, comprising: a plurality of memory cell columns, a plurality of bit line pairs, each connected to a corresponding one of said plurality of memory cell columns, a plurality of signal holding means, each connected to a corresponding one of said plurality of bit line pairs, for holding a data signal read out from said corresponding one memory cell column, a signal transmission line pair for transmitting a data signal provided from said plurality of signal holding means, a plurality of serial transfer means, each connected between said plurality of signal holding means and said signal transmission line pair, for transferring a data signal held in a corresponding one of said plurality of signal holding means to said signal transmission line pair, serial selecting means responsive to the serial out clock signal for selecting in series said plurality of serial transfer means, said plurality of serial transfer means responsive to said serial selecting means for transferring in series a data signal held by said plurality of signal holding means to said signal transmission line pair, equalize means connected to said signal transmission line pair for equalizing said signal transmission line pair, amplifying means responsive to the serial out clock signal for amplifying said data signal transmitted via said signal transmission line pair, and disconnecting means for electrically disconnecting said signal transmission line pair and said amplifying means after said amplifying means commences amplifying operation, said equalized means commencing equalized operation of said signal transmission line pair after said disconnecting means is operated.

Claim 13

The serial access memory device according to claim 10, wherein said plurality of signal holding means comprises a plurality of latch circuit means, each connected to said plurality of bit line pairs, for latching a data signal read out from said corresponding one memory cell column.

Claim 14

The serial access memory device according to claim 11, wherein said signal transmission line pair comprises a serial bus line pair for transmitting a data signal transferred in series from said plurality of serial transfer means.