High-speed magnitude comparator circuit

Claim 2

A high speed magnitude comparator circuit, comprising: a plurality of logic cells corresponding to a plurality of bit positions in first and second operands except for a least significant bit position, each logic cell providing a first output signal equal to a logical OR of a complement of a corresponding bit of said first operand and a corresponding bit of said second operand, and a second output signal equal to a logical AND of said complement of said corresponding bit of said first operand and said corresponding bit of said second operand; a least-significant logic cell for providing a first output signal equal to a logical OR of a complement a least significant bit of said first operand and a least significant bit of said second operand, and a second output signal equal to a logical OR of said complement of said least significant bit of said first operand and said least significant bit of said second operand; a signal line for conducting an output signal; a pullup portion including a plurality of columns of transistors, for coupling said signal line to a first power supply voltage terminal in response to said first and second output signals of both said plurality of logic cells and said least-significant logic cell indicating that said first operand is greater than said second operand; and a pulldown portion including a plurality of columns of transistors, for coupling said signal line to a second power supply voltage terminal in response to said first and second output signals of both said plurality of logic cells and said least-significant logic cell indicating that said first operand is less than or equal to said second operand.

Claim 3

The high speed magnitude comparator circuit of claim 1, wherein said pullup portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between a first power supply voltage terminal and said signal line and receiving one of said plurality of first signals corresponding to said bit position.

Claim 4

The high speed magnitude comparator circuit of claim 2, wherein said plurality of columns of transistors comprises a first column corresponding to said most significant bit position, including a first transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first output signal corresponding to said most significant bit position, and a second current electrode coupled to said signal line.

Claim 5

The high speed magnitude comparator circuit of claim 3, wherein said plurality of columns of transistors comprises a second column of transistors, said second column comprising: a second transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving a second signal corresponding to said most-significant bit position, and a second current electrode; and a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving a first signal corresponding to a next-most-significant bit position, and a second current electrode coupled to said signal line.

Claim 6

The high speed magnitude comparator circuit of claim 2, wherein each transistor in said plurality of columns of transistors in said pullup portion is a P-channel MOS transistor.

Claim 7

The high speed magnitude comparator circuit of claim 1, wherein said pulldown portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between a second power supply voltage terminal and said signal line and receiving one of either said plurality of second signals or said third signal, corresponding to said bit position.

Claim 8

The high speed magnitude comparator circuit of claim 6, wherein said pulldown portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between said signal line and a second power supply voltage terminal and receiving either one of said plurality of second signals or said third signal, corresponding to said bit position.

Claim 9

The high speed magnitude comparator circuit of claim 7, wherein said plurality of columns of transistors comprises a first column corresponding to said most significant bit position, including a first transistor having a first current electrode coupled to said signal line, a control electrode for receiving said second output signal corresponding to said most significant bit position, and a second current electrode coupled to said second power supply voltage terminal.

Claim 10

The high speed magnitude comparator circuit of claim 8, wherein said plurality of columns of transistors comprises a second column of transistors, said second column comprising: a second transistor having a first current electrode coupled to said signal line, a control electrode for receiving a second signal corresponding to a next-most-significant bit position, and a second current electrode; and a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving a first signal corresponding to said most-significant bit position, and a second current electrode coupled to said second power supply voltage terminal.

Claim 11

The high speed magnitude comparator circuit of claim 7, wherein each transistor in said plurality of columns of transistors in said pulldown portion is an N-channel MOS transistor.

Claim 12

A high speed magnitude comparator circuit, comprising: first and second input ports respectively receiving first and second operands, each of said first and second operands having a predetermined number of bits ordered from a most-significant bit to a least-significant bit; first logic means coupled to said first and second input ports, for providing a plurality of first signals corresponding to each of said bit positions of said first and second operands, each first signal being a logical OR of a complement of a corresponding bit of said first operand and a corresponding bit of said second operand; second logic means coupled to said first and second input ports, for providing a plurality of second signals corresponding to each of said bit positions of said first and second operands except for said first bit position, each second signal being a logical AND of a complement a corresponding bit of said first operand and a corresponding bit of said second operand; third logic means coupled to said first and second input ports, for providing a third signal equal to a logical OR of a complement of said least significant bit of said first operand and said least significant bit of said second operand; a signal line coupled to said first, second, and third logic portions for conducting an output signal of the magnitude comparator thereon; a pullup portion coupled to said first, second, and third logic portions and to said signal line, for coupling said signal line to a first power supply voltage terminal in response to a value of said first operand exceeding a value of said second operand; and a pulldown portion coupled to said first, second, and third logic portions and to said signal line, for coupling said signal line to a second power supply voltage terminal in response to said value of said first operand being less than or equal to said value of said second operand.

Claim 13

A high speed magnitude comparator circuit, comprising: first and second input ports respectively receiving first and second operands, each of said first and second operands having a predetermined number of bits ordered from a most-significant bit to a least-significant bit; first logic means coupled to said first and second input ports, for providing a plurality of first signals corresponding to each of said bit positions of said first and second operands, each first signal being a logical OR of a complement of a corresponding bit of said first operand and a corresponding bit of said second operand; second logic means coupled to said first and second input ports, for providing a plurality of second signals corresponding to each of said bit positions of said first and second operands except for said first bit position, each second signal being a logical AND of a complement a corresponding bit of said first operand and a corresponding bit of said second operand; third logic means coupled to said first and second input ports, for providing a third signal equal to a logical OR of a complement of said least significant bit of said first operand and said least significant bit of said second operand; a signal line coupled to said first, second, and third logic portions for conducting an output signal of the magnitude comparator thereon; a pullup portion coupled to said first, second, and third logic portions and to said signal line, for coupling said signal line to a first power supply voltage terminal in response to a value of said first operand exceeding a value of said second operand; and a pulldown portion coupled to said first, second, and third logic portions and to said signal line, for coupling said signal line to a second power supply voltage terminal in response to said value of said first operand being less than or equal to said value of said second operand.

Claim 14

The high speed magnitude comparator circuit of claim 11, wherein said pullup portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between a first power supply voltage terminal and said signal line and receiving one of said plurality of first signals corresponding to said bit position.

Claim 15

The high speed magnitude comparator circuit of claim 12, wherein said plurality of columns of transistors comprises a first column corresponding to said most significant bit position, including a first transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first output signal corresponding to said most significant bit position, and a second current electrode coupled to said signal line.

Claim 16

The high speed magnitude comparator circuit of claim 13, wherein said plurality of columns of transistors comprises a second column of transistors, said second column comprising: a second transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving a second signal corresponding to said most-significant bit position, and a second current electrode; and a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving a first signal corresponding to a next-most-significant bit position, and a second current electrode coupled to said signal line.

Claim 17

The high speed magnitude comparator circuit of claim 12, wherein each transistor in said plurality of columns of transistors in said pullup portion is a P-channel MOS transistor.

Claim 18

The high speed magnitude comparator circuit of claim 11, wherein said pulldown portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between a second power supply voltage terminal and said signal line and receiving one of either said plurality of second signals or said third signal, corresponding to said bit position.

Claim 19

The high speed magnitude comparator circuit of claim 16, wherein said pulldown portion comprises a plurality of columns of transistors, each column of transistors corresponding to one of said bit positions, each column of transistors including at least one transistor serially coupled between said signal line and a second power supply voltage terminal and receiving either one of said plurality of second signals or said third signal, corresponding to said bit position.

Claim 20

The high speed magnitude comparator circuit of claim 17, wherein said plurality of columns of transistors comprises a first column corresponding to said most significant bit position, including a first transistor having a first current electrode coupled to said signal line, a control electrode for receiving said second output signal corresponding to said most significant bit position, and a second current electrode coupled to said second power supply voltage terminal.

Claim 21

The high speed magnitude comparator circuit of claim 18, wherein said plurality of columns of transistors comprises a second column of transistors, said second column comprising: a second transistor having a first current electrode coupled to said signal line, a control electrode for receiving a second signal corresponding to a next-most-significant bit position, and a second current electrode; and a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving a first signal corresponding to said most-significant bit position, and a second current electrode coupled to said second power supply voltage terminal.

Claim 22

The high speed magnitude comparator circuit of claim 17, wherein each transistor in said plurality of columns of transistors in said pulldown portion is an N-channel MOS transistor.

Claim 23

A high speed magnitude comparator circuit comprising: first logic means for providing a first signal equal to a logical OR of a complement of a least significant bit of a first operand and a least significant bit of a second operand; second logic means for providing a second signal equal to a logical OR of a complement of a next-least significant bit of a first operand and a next-least significant bit of a second operand; third logic means for providing a third signal equal to a logical AND of a complement of a next-least significant bit of a first operand and a next-least significant bit of a second operand; fourth logic means for providing a fourth signal equal to a logical OR of a complement of a least significant bit of said first operand and a least significant bit of said second operand; a signal line for conducting an output signal; a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving said second signal, and a second current electrode coupled to said signal line; a second transistor having a first current electrode coupled to said signal line, a control electrode for receiving said third signal, and a second current electrode coupled to a second power supply voltage terminal; a third transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said third signal, and a second current electrode; a fourth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said first signal, and a second current electrode coupled to said signal line; a fifth transistor having a first current electrode coupled to said signal line, a control electrode for receiving said fourth signal, and a second current electrode; and a sixth transistor having a first current electrode coupled to said second current electrode of said fifth transistor, a control electrode for receiving said second signal, and a second current electrode coupled to said second power supply voltage terminal.

Claim 24

A high speed magnitude comparator circuit comprising: first logic means for providing a first signal equal to a logical OR of a complement of a least significant bit of a first operand and a least significant bit of a second operand; second logic means for providing a second signal equal to a logical OR of a complement of a next-least significant bit of a first operand and a next-least significant bit of a second operand; third logic means for providing a third signal equal to a logical AND of a complement of a next-least significant bit of a first operand and a next-least significant bit of a second operand; fourth logic means for providing a fourth signal equal to a logical OR of a complement of a least significant bit of said first operand and a least significant bit of said second operand; a signal line for conducting an output signal; a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving said second signal, and a second current electrode coupled to said signal line; a second transistor having a first current electrode coupled to said signal line, a control electrode for receiving said third signal, and a second current electrode coupled to a second power supply voltage terminal; a third transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said third signal, and a second current electrode; a fourth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said first signal, and a second current electrode coupled to said signal line; a fifth transistor having a first current electrode coupled to said signal line, a control electrode for receiving said fourth signal, and a second current electrode; and a sixth transistor having a first current electrode coupled to said second current electrode of said fifth transistor, a control electrode for receiving said second signal, and a second current electrode coupled to said second power supply voltage terminal.

Claim 25

The high speed magnitude comparator circuit of claim 21, wherein said first, third, and fourth transistors are P-channel MOS transistors, and wherein said second, fifth, and sixth transistors are N-channel MOS transistors.

Claim 26

The high speed magnitude comparator circuit of claim 21, wherein said first and second logic means each comprise: an inverter having an input terminal for receiving a corresponding bit of said second operand, and an output terminal; and a NAND gate having a first input terminal for receiving a corresponding bit of said first operand, a second input terminal coupled to said output terminal of said inverter, and an output terminal for providing a corresponding one of said first and second signals.