Time-division multiplex communication system with a synchronizing circuit at the receiving end which responds to the coding of words inserted in the transmitted information

Claim 2

Time-division multiplex communication system comprising: a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device at a receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) checks all n-bit groups (X j to X j-n-1 ) which begin with any one (X j ) of the n successive bits of the received bit sequence by successively checking in parallel n-bit groups and by independently checking each n-bit group.

Claim 3

A system as claimed in claim 1, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) calculates a syndrome (S 1 to S n-k ) for each of the n-bit groups (X j to X j-n-1 ) on the basis of a parity check matrix of the linear block code used and, if the syndrome (S 1 to S n-k ) is zero, provides a signal indicating the presence of one of the n-bit words.

Claim 4

Time-division multiplex communication system comprising: a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device (SR1, SR2, N 1 to N n-k , LS) at a receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) successively checks all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the n successive bits of the received bit sequence, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) calculates a syndrome (S 1 to S n-k ) is zero, provides a signal indicating the presence of one of the n-bit words, and wherein the checking device (SR1, SR2, N 1 to N n-k , LS) contains a network (N i ) for each component (S i ) of the syndrome (S 1 to S n-k ) which calculates one component (S i ) of the syndrome (S 1 to S n-k ) from the n-bit bit group (X j to X j+n-1 ) to be checked, a logic (LS) which determines from the calculated components of the syndrome (S 1 to S n-k ) whether the syndrome (S 1 S n-k ) is zero, and a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit group is completed.

Claim 5

Time-division multiplex communication system comprising: a transmitting device which regularly encodes an n-bit word in a linear block code into a bit sequence to be transmitted, and a checking device (SR1, SR2, N 1 to N n-k , LS) at a receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) successively checks all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the n successive bits of the received bit sequence, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) calculates a syndrome (S 1 to S n-k ) is zero, provides a signal indicating the presence of one of the n-bit words, and wherein the checking device (SR1, SR2, N 1 to N n-k , LS) contains a network (N i ) for each component (S i ) of the syndrome (S 1 to S n-k ) which calculates one component (S i ) of the syndrome (S 1 to S n-k ) from the n-bit bit group (X j to X j+n-1 ) to be checked, a logic (LS) which determines from the calculated components of the syndrome (S 1 to S n-k ) whether the syndrome (S 1 S n-k ) is zero, and a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit group is completed.

Claim 6

A system as claimed in claim 3, wherein the checking device (SR1, SR2, N 1 to N n-k , LS) processes the received bit sequence at the bit rate (C).

Claim 7

A system as claimed in claim 4, wherein in the checking device (SR1, SR2, N 1 N n-k , LS), each bit of an n-bit bit group (X j to X j+n-1 ) to be checked is fed into each of the networks (N i ) in parallel, and that each of the networks (N i ) calculates its component (S i ) of the syndrome (S 1 to S n-1 ) in several successive stages by exclusive-ORing its input bits in accordance with the parity check matrix.

Claim 8

A system as claimed in claim 5, wherein the received bit sequence passes through an (N-1)-bit shift register (SR1) which provides an n-bit bit group (X j to X j+n-1 ) to the networks (N 1 to N n-k ) on each pulse of the bit rate (C).

Claim 9

A system as claimed in claim 6, wherein each network (N i ) is fed only with those bits of the n-bit bit group (X j to X j+n-1 ) for which the associated parity check matrix components to be used in the network (N i ) are nonzero.

Claim 10

A system as claimed in claim 7, wherein those networks (N i ) whose number (M i ) of stages (ST 1 to ST 4 is less than the maximum number of stages required in any of the networks have additional stages including delay elements (E 2 ), so that all networks (N 1 to N n-k ) provide their components (S i ) of the syndrome (S 1 to S n-k ) at their outputs simultaneously.

Claim 13

The method of claim 9, wherein the successively checking step comprises the steps of: calculating a syndrome (S 1 to S n-k ) for each of the n-bit bit groups on the basis of a parity check matrix of the linear block code; and if the syndrome is zero, providing a signal indicating the presence of one of the n-bit words.

Claim 16

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits, by successively checking in parallel n-bit groups and by independently checking each n-bit group.

Claim 17

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits, by successively checking in parallel n-bit groups and by independently checking each n-bit group.

Claim 18

The checking device of claim 12, wherein the checking means calculates a syndrome (S 1 to S n-k ) for each of the n-bit groups on the basis of a parity check matrix of the linear block code used and, if the syndrome is zero, provides a signal indicative of the presence of one of the n-bit words.

Claim 19

A system as claimed in claim 12, wherein processing within the checking means takes place at a bit rate (C) of the received bit sequence.

Claim 20

The checking device of claim 12, wherein in the checking means, an n-bit group (X j to X j+n-1 ) to be checked is fed into each of a plurality of networks (N i ) in parallel, and that each of the networks calculates its component (S i ) of the syndrome (S 1 to S n-k ) in several successive stages by exclusive-ORing its input bits in accordance with a parity check matrix.

Claim 21

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits; a network (N i ) for each component (S i ) of the syndrome (S 1 to S n-k ) which calculates one component (S i ) of the syndrome (S 1 to S n-k ) from the n-bit group (X j to X j+n-1 ) to be checked; a logic means (LS) which determines from the calculated components of the syndrome (S 1 to S n-l ) whether the syndrome is zero; and a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit bit group is completed.

Claim 22

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits; a network (N i ) for each component (S i ) of the syndrome (S 1 to S n-k ) which calculates one component (S i ) of the syndrome (S 1 to S n-k ) from the n-bit group (X j to X j+n-1 ) to be checked; a logic means (LS) which determines from the calculated components of the syndrome (S 1 to S n-l ) whether the syndrome is zero; and a delay circuit (SR2) which delays the received bit sequence until the check of an n-bit bit group is completed.

Claim 23

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits; wherein the received bit sequence passes through the storage means comprising an (n-1)-bit shift register (SR1), which provides an n-bit bit group (X j to X j+n-1 ) to a plurality of networks (N 1 to N n-k ) on each pulse of a bit clock (C); wherein each network (N i ) is fed only with those bits of the n-bit group (X j to X j+n-1 ) for which the associated parity check matrix components to be used in the network (N i ) are non-zero; wherein the networks (N i ) whose number (M i ) of stages ST 4 to ST 1 ) is less than a maximum number of stages required in any of the networks of additional stages, including delay elements (E 2 ), so that all networks (N 1 to N n-k ) provide their components (S i ) of the syndrome (S 1 ) to S n-k ) at their outputs simultaneously.

Claim 24

A checking device for a time-division multiplex communication system having a transmitting device which regularly inserts an n-bit word coded in a linear block code into a bit sequence to be transmitted, comprising: storage means, responsive to the transmitted bit sequence, for storing the bits thereof for providing the stored bits; and checking means, responsive to selected stored bits, for checking groups of n successive bits as to whether they are coded in the block code by successively checking all n-bit groups (X j to X j+n-1 ) which begin with any one (X j ) of the successive bits; wherein the received bit sequence passes through the storage means comprising an (n-1)-bit shift register (SR1), which provides an n-bit bit group (X j to X j+n-1 ) to a plurality of networks (N 1 to N n-k ) on each pulse of a bit clock (C); wherein each network (N i ) is fed only with those bits of the n-bit group (X j to X j+n-1 ) for which the associated parity check matrix components to be used in the network (N i ) are non-zero; wherein the networks (N i ) whose number (M i ) of stages ST 4 to ST 1 ) is less than a maximum number of stages required in any of the networks of additional stages, including delay elements (E 2 ), so that all networks (N 1 to N n-k ) provide their components (S i ) of the syndrome (S 1 ) to S n-k ) at their outputs simultaneously.