Method and apparatus for detecting a predetermined bit pattern within a serial bit stream

Claim 1

A method for detecting a predetermined pattern of n bits included within a serial bit stream, said n bits being adjacent or distributed over the bit stream according to a predetermined sequence, and representing a unique word (16) chosen to contain m different valid subsets (18) of nʹ successive bits (with 1 < m < n and 1 < nʹ < n), where each of such a subset is said to be valid provided it is determined in a unique manner by its position within the unique word and thus permits to determine the (n-nʹ) remaining bits of said unique word, which follow the cited nʹ bits, said method including, among its steps: - detecting subsets of nʹ bits of the serial bit stream (14); - comparing each detected subset of nʹ bits to all of the m valid subsets to identify the event of having detected a particular subset among the m valid subsets, and on said event; - verifying if the entire unique word has been received, by determining among the received bits, each of the potential bits of said unique word, and comparing consecutively each of those potential bits, to each of the ((n-nʹ) bits which follow the nʹ bits of the particular subset of the unique word which has already been detected; - counting the number of successive matches that occur during the comparison step between the couples of bits being compared, and when a predetermined number of matches is reached, deciding that the unique word has effectively been detected, and accordingly, raising an appropriate signal, which can in turn start an action or set an adequate status within a circuit.

Claim 2

A method for detecting a predetermined pattern of n bits included within a serial bit stream, said n bits being adjacent or distributed over the bit stream according to a predetermined sequence, and representing a unique word (16) chosen to contain m different valid subsets (18) of nʹ successive bits (with 1 < m < n and 1 < nʹ < n), where each of such a subset is said to be valid provided it is determined in a unique manner by its position within the unique word and thus permits to determine the (n-nʹ) remaining bits of said unique word, which follow the cited nʹ bits, said method including, among its steps: - detecting subsets of nʹ bits of the serial bit stream (14); - comparing each detected subset of nʹ bits to all of the m valid subsets to identify the event of having detected a particular subset among the m valid subsets, and on said event; - verifying if the entire unique word has been received, by determining among the received bits, each of the potential bits of said unique word, and comparing consecutively each of those potential bits, to each of the ((n-nʹ) bits which follow the nʹ bits of the particular subset of the unique word which has already been detected; - counting the number of successive matches that occur during the comparison step between the couples of bits being compared, and when a predetermined number of matches is reached, deciding that the unique word has effectively been detected, and accordingly, raising an appropriate signal, which can in turn start an action or set an adequate status within a circuit.

Claim 5

An apparatus for the implementation of the method defined in one of the claims 1-3, said apparatus being located at a reception node where it receives, at a rate defined by the received clock signal, the serial bit stream comprising the data bits and the bits contained in the unique word (16), said apparatus including: - first detection means (22) for the detection of nʹ bits of the bit stream, said first detecting means being connected to first decoding means (28) who generate a "VALID SUBSET" signal when the detected subset of nʹ bits is decoded as being a valid subset; - storage means (24) containing m different subsets of (n-nʹ) consecutive bits of the unique word, each of said subsets being equal to the unique word minus a said particular valid subset of nʹ bits, said storage means being addressed by the nʹ bits output by the first detecting means (22) and delivering at their output the specific subset of (n-nʹ) bits corresponding to the address applied to the entry of said storage means, upon receipt of said "VALID SUBSET" signal transmitted by said decoding means; - a second detecting means (38) for the detection, in the received serial bit stream, of the next potential bits of the unique word; - comparison means (36) performing the comparison between, on the one hand, the said potential bits of the unique word who are being provided by said second detecting means, and on the other hand, the successive bits included in the specific subset of (n-nʹ) bits provided by said storage means, said comparison means generating at their output, an "EQUALITY PULSE" equal to "one" each time a match occurs between two compared bits, and to "zero" each time a mismatch occurs; - first counting means (54) connected to the output of the comparison means and performing the counting of said matches; - second decoding means (56) connected to said counting means and performing the decoding of a predetermined number reached by the first counting means, whereupon said second decoding means raise their output line in order to indicate that the unique word has been detected.

Claim 8

An apparatus according to one of the claims 4-6, wherein said second detection means (138) include one discrete eight-bit shift register (160) and one 185-bit shift register (162) connected in series ahead of said first detection means.

Claim 9

An apparatus according to one of the claims 4-7, wherein said first decoding means (128) include combinatorial logic receiving the content of said b21, b31, b41, b51 cells as parallel inputs, and delivering through an eight-bit "valid address" shift register, a read command transmitted to storage means (124) when four bits applied as an address to said first decoding means correspond to a valid subset.

Claim 10

An apparatus according to claims 4-8, wherein said storage means include a Read Only Storage (ROS) (196) addressed by a valid subset and delivering for each address, a byte containing the eight remaining bits of the synchronization pattern, corresponding to the applied address, said byte being transferred, upon receipt of a "new synchronization search" signal, to aSynchronization Pattern Shift Register (SYNREG) (200) under control of a logic SYNREG CONTROL CIRCUIT.

Claim 11

An apparatus according to claims 4-9, wherein said comparison means include an AND gate (137) performing an AND function between the last detected potential bit (b11) of the synchronization pattern, the bit of said synchronization pattern which immediately follows the current valid subset, and a "193 decoded" signal provided by said up-counter (C1), said AND gate providing an "EQUALITY PULSE" to said first counting means.