Read-only memory

Claim 1

A read-only memory device comprising columns of memory cell arrays, a plurality of adjacent banks formed in rows by dividing each of said columns of the memory cell arrays along the length of said columns, sub-bit lines disposed between adjacent banks and connected to a transistor of each memory cell in each of the adjacent banks, main-bit lines disposed between every other two columns of the memory cell arrays and extending parallel to the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks in a common row, said sets of three sub-bit lines comprising a center sub-bit line and two laterally opposite outer sub-bit lines, one end of each said center sub-bit line being connected to a first main-bit line through a first selector transistor, and an other end of the center sub-bit line being connected to a second main-bit line through a second selector transistor, both ends of one of the two laterally opposite outer sub-bit lines being connected directly to the first main-bit line, and both ends of the other one of the two laterally opposite outer sub-bit lines being connected directly to the second main-bit line, whereby in selecting a particular memory transistor of one of said pair of adjacent banks, the first selector transistor is turned off and the second selector transistor is turned on, and in selecting a particular memory transistor belonging to an opposite side of said pair of adjacent banks, the first selector transistor is turned on and the second selector transistor is turned off.