Microprocessor capable of transferring data without intermediating execution unit

Claim 1

A microprogram-controlled microprocessor comprising: an execution controller for generating a block transfer start signal when a decoder decodes a block transfer instruction, said execution controller being brought into a condition of being inhibited from executing a microprogram when said block transfer start signal is generated; a data controller having a read operand register coupled to an external data bus so as to fetch data on said external data bus, and a write operand register coupled to said external data bus so as to output data stored in the write operand register to said external bus, said data controller being controlled by said block transfer start signal so that said write operand register is directly coupled to said read operand register so as to directly receive data registered in said read operand register without intermediating said execution controller, said data controller generating a ready signal at each time that said read operand register becomes empty; and an access controller having a transfer source length register and a transfer destination length register which are respectively set with a transfer source length and a transfer destination length when said decoder decodes said block transfer instruction, said transfer source length register and said transfer destination length register being decremented at each time that data is transferred through said read operand register and said write operand register, said access controller generating an access request signal when neither said transfer source length register nor said transfer destination length register is zero and when said ready signal is active, so that if said data controller receives said access request signal when said ready signal is active, said data controller causes said read operand register to fetch data on said external data bus so that the data fetched in said read operand register is transferred to said write operand register, and when said ready signal is active but said access request signal has not yet been activated, said data controller causes said write operand register to transfer the data fetched in said write operand register to said external data bus, whereby data is continuously and repeatedly transferred through said read operand register and said write operand register without intermediating said execution controller.