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US5278798A
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1991-04-18
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Granted: 1994-01-11
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Expires: 2011-04-18
Abstract
Abstract The semiconductor memory device comprises first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when the second power source voltage becomes higher by a predetermined value than the first power source voltage; a power source switching circuit for controlling the memory device so that power is supplied from the second power source, in response to the detection signal; and a data hold control circuit for controlling the memory device so that data are kept stored therein in response to the detection signal. Since these circuits are incorporated inside the chip, the packaging efficiency or density of the memory devices can be improved when the memory devices are integrated on a semiconductor substrate.
Inventors
- 👤 Naokazu Miyawaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:38
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/141; G11C11/00; G11C11/21; G11C11/34
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
113 words
A semiconductor memory device, comprising: first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when voltage outputted from the first power source becomes relatively lower than an absolute valve inherently determined within the device; a power source switching circuit for controlling the memory device so that power is supplied from the second power source, when said detection circuit outputs the detection signal; and a data hold control circuit for controlling the memory device so that data can be kept stored, when said detection circuit outputs the detection signal, said detection circuit and said power source switching circuit being comprised of MOS circuits.
Claim 2
Dependent Claim
113 words
A semiconductor memory device, comprising: first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when voltage outputted from the first power source becomes relatively lower than an absolute valve inherently determined within the device; a power source switching circuit for controlling the memory device so that power is supplied from the second power source, when said detection circuit outputs the detection signal; and a data hold control circuit for controlling the memory device so that data can be kept stored, when said detection circuit outputs the detection signal, said detection circuit and said power source switching circuit being comprised of MOS circuits.
Claim 3
Dependent Claim
16 words
The semiconductor memory device of claim 1, wherein the second power source is a back-up battery.
Claim 4
Dependent Claim
63 words
The semiconductor memory device of claim 1, wherein said power source switching circuit comprises a first transistor connected between an output terminal and the first power source and turned off when said detection circuit outputs the detection signal, and a second transistor switch connected between the output terminal and the second power source and turned on when voltage of the output terminal drops.
Claim 5
Dependent Claim
33 words
The semiconductor memory device of claim 1, wherein said data hold control circuit is a gate for generating a logical product signal of an output of said detection signal and a refresh signal.
Claim 6
Dependent Claim
18 words
The semiconductor memory device of claim 1, wherein said absolute value is a threshold voltage of a transistor.
Claim 7
Dependent Claim
111 words
A semiconductor memory device, comprising: first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when voltage outputted from the first power source becomes lower than a predetermined value, the detection circuit outputting the detection signal independently of a value of a voltage output by the second power source; a power source switching circuit, responsive to the detection signal, for supplying power from the second power source, when the detection circuit outputs the detection signal; and a data hold control circuit for controlling the memory device so that data can be kept stored, when said detection circuit outputs the detection signal.
Claim 8
Dependent Claim
111 words
A semiconductor memory device, comprising: first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when voltage outputted from the first power source becomes lower than a predetermined value, the detection circuit outputting the detection signal independently of a value of a voltage output by the second power source; a power source switching circuit, responsive to the detection signal, for supplying power from the second power source, when the detection circuit outputs the detection signal; and a data hold control circuit for controlling the memory device so that data can be kept stored, when said detection circuit outputs the detection signal.
References Cited (Backward Citations)
US4313180A
Cited
US4908790A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-10 | 1997-07-12 | 1998-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-10 | 2001-07-12 | 2002-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-10 | 2005-07-12 | 2006-01-11 | $7700.00 | Window Closed / Lapsed |