Patent US5278784A successfully refreshed from Google Patents.
US5278784A
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Non-volatile memory
Assignee: Sharp Corp
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Filing: 1992-11-24
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Granted: 1994-01-11
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Expires: 2012-11-24
Abstract
Abstract A non-volatile programmable memory having: a plurality of unit cells disposed therein, each of said unit cells including an anti-fuse that can write in data by electrically breaking down an insulating film, a select transistor individually connected to said anti-fuse, and a wiring connected to each anti-fuse; and an auxiliary transistor connected between mutually adjacent unit cells, said auxiliary transistor having a source region and a drain region respectively connected between said anti-fuse and said select transistor together incorporated in mutually adjacent unit cells.
Inventors
- 👤 Hiroshi Ishihara
- 👤 Norihiro Tokuyama
- 👤 Masaru Yuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:09
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
88 words
A non-volatile programmable memory having: a plurality of unit cells disposed therein, each of said unit cells including an anti-fuse that can write in data by electrically breaking down an insulating film of the anti-fuse, a select transistor individually connected to said anti-fuse, and a wiring connected to each of anti-fuse; and an auxiliary transistor connected between mutually adjacent unit cells, said auxiliary transistor having a source region and a drain region respectively connected between said anti-fuse and said select transistor together incorporated in mutually adjacent unit cells.
Claim 2
Dependent Claim
88 words
A non-volatile programmable memory having: a plurality of unit cells disposed therein, each of said unit cells including an anti-fuse that can write in data by electrically breaking down an insulating film of the anti-fuse, a select transistor individually connected to said anti-fuse, and a wiring connected to each of anti-fuse; and an auxiliary transistor connected between mutually adjacent unit cells, said auxiliary transistor having a source region and a drain region respectively connected between said anti-fuse and said select transistor together incorporated in mutually adjacent unit cells.
Claim 3
Dependent Claim
32 words
A non-volatile programmable memory of claim 1, wherein both the select transistor and the auxiliary transistor respectively comprise a gate electrode, said electrodes of both being formed on an identical conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-10 | 1997-07-12 | 1998-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-10 | 2001-07-12 | 2002-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-10 | 2005-07-12 | 2006-01-11 | $7700.00 | Window Closed / Lapsed |