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US5277985A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits

Assignee: Cornell Research Foundation Inc
•
Filing: 1991-11-12
•
Granted: 1994-01-11
•
Expires: 2011-11-12
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Abstract

Abstract The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60° and 80° C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450° to 650° C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

Inventors

  • 👤 Jian Li
  • 👤 Evan Colgan
  • 👤 James W. Mayer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 22:15
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/055; H10W20/038; H10W20/039; H10W20/064; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 133 words
A product by process comprising low-temperature, self-encapsulated, copper interconnect lines on substrates of Ultra-Large Scale Integration (ULSI) circuits, the interconnect lines of said ultra-large scale integrated (ULSI) circuits having a titanium nitride film defined by the process comprising the steps of: (a) alloying copper with titanium to provide a material for forming interconnect lines upon a substrate; (b) forming said interconnect lines upon said substrate; (c) after forming the interconnect lines on the substrate, utilizing a fast heating rate of greater than 50° C./minute, to anneal the interconnect lines so that surface diffusion dominates over internal nucleation, thus providing a surface rich in titanium upon said interconnect lines; and (c) utilizing an annealing ambient of ammonia below approximately 650° C., to provide chemical formation of a titanium nitride film about said interconnect lines.
Claim 2
Dependent Claim 133 words
A product by process comprising low-temperature, self-encapsulated, copper interconnect lines on substrates of Ultra-Large Scale Integration (ULSI) circuits, the interconnect lines of said ultra-large scale integrated (ULSI) circuits having a titanium nitride film defined by the process comprising the steps of: (a) alloying copper with titanium to provide a material for forming interconnect lines upon a substrate; (b) forming said interconnect lines upon said substrate; (c) after forming the interconnect lines on the substrate, utilizing a fast heating rate of greater than 50° C./minute, to anneal the interconnect lines so that surface diffusion dominates over internal nucleation, thus providing a surface rich in titanium upon said interconnect lines; and (c) utilizing an annealing ambient of ammonia below approximately 650° C., to provide chemical formation of a titanium nitride film about said interconnect lines.
Claim 3
Dependent Claim 29 words
The product by process in accordance with claim 1, wherein said chemical formation of step (d) is accomplished using an ammonia atmosphere at an approximate temperature of 550° C.
Claim 4
Dependent Claim 39 words
The product by process in accordance with claim 1, wherein said step (c) of providing a titanium rich surface film includes heating said interconnect lines and said substrate at an approximate ramping rate of between 60° and 80° C./minute.
Claim 5
Dependent Claim 17 words
The product by process in accordance with claim 3, wherein said ramping rate is approximately 70° C./minute.
Claim 6
Dependent Claim 28 words
The product by process in accordance with claim 1, wherein said alloying step (a) alloys said copper with titanium in an approximate 10 atomic weight percentage of titanium.

References Cited (Backward Citations)

US4151325A Cited
US4570328A Cited
US4546050A Cited
US4690871A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-01-10 1997-07-12 1998-01-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-01-10 2001-07-12 2002-01-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-01-10 2005-07-12 2006-01-11 $7700.00 Window Closed / Lapsed

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