Destination control logic for arithmetic and logic unit for digital data processor

Claim 2

A data path for use in a processor in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including a plurality of source data means for providing source data signals, said data path including: A. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; B. a first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; C. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; D. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and E. control means including: i. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals; and ii. destination control means connected to said source control means and said destination data selection means for generating, in response to said first and second source control signals and said micro-control signals, destination control signals which identify one of said first source data means or said second source data means to cause said destination data selection means to transfer said processed data signals to the identified one of said source data means.

Claim 3

A data path as defined in claim 1 in which said destination control means includes a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for coupling one of said first source control signals or said second source control signals to said output means as said destination control signals.

Claim 4

A data path as defined in claim 2 wherein said source control means includes first and second source control signal generator means each for generating one of said first and second source control signals, each said first and second source control signal generator means including decoder means for receiving respective micro-control signals and for generating, in response thereto, respective first and second source control signals.

Claim 5

A data path as defined in claim 3 wherein each of said first and second source control signal generator means includes a decoder for receiving said micro-control signals and generating, in response thereto, first and second source signals and a latch connected to said respective decoder for latching the first and second source control signals.

Claim 6

A data path as defined in claim 4 wherein said processor includes a plurality of registers, said control means further including counter means having a plurality of states each identifying one of said registers, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals.

Claim 7

A data path for use in a processor in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including a plurality of source data means, including a plurality of registers, for providing source data signals, said data path including: A. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; B. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; C. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; D. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and E. control means including: i. counter means having a plurality of states each identifying one of said registers, ii. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals, said first and second source control means each including a decoder for receiving said micro-control signals and generating, in response thereto, said first and second source control signals and a latch connected to said respective decoder for latching the first and second source control signals, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals; and iii. destination control means comprising a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for selecting one of said first source control signals or said second source control signals and coupling the selected source control signals to said output means as said destination control signals to cause said destination data selection means to transfer said processed data signals to the source data means identified by said selected one of said first source control signals or said second source control signals.

Claim 8

A data path for use in a processor in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including a plurality of source data means, including a plurality of registers, for providing source data signals, said data path including: A. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; B. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; C. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; D. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and E. control means including: i. counter means having a plurality of states each identifying one of said registers, ii. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals, said first and second source control means each including a decoder for receiving said micro-control signals and generating, in response thereto, said first and second source control signals and a latch connected to said respective decoder for latching the first and second source control signals, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals; and iii. destination control means comprising a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for selecting one of said first source control signals or said second source control signals and coupling the selected source control signals to said output means as said destination control signals to cause said destination data selection means to transfer said processed data signals to the source data means identified by said selected one of said first source control signals or said second source control signals.

Claim 9

A processor for use in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including: A. a plurality of source data means for providing source data signals; B. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; C. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; D. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; E. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and F. control means including: i. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals; and ii. destination control means connected to said source control means and said destination data selection means for generating, in response to said first and second source control signals and said micro-control signals, destination control signals which identify one of said first source data means or said second source data means to cause said destination data selection means to transfer said processed data signals to the identified one of said source data means.

Claim 10

A processor for use in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including: A. a plurality of source data means for providing source data signals; B. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; C. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; D. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; E. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and F. control means including: i. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals; and ii. destination control means connected to said source control means and said destination data selection means for generating, in response to said first and second source control signals and said micro-control signals, destination control signals which identify one of said first source data means or said second source data means to cause said destination data selection means to transfer said processed data signals to the identified one of said source data means.

Claim 11

A processor as defined in claim 7 in which said destination control means includes a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for coupling one of said first source control signals or said second source control signals to said output means as said destination control signals.

Claim 12

A processor as defined in claim 8 wherein said source control means includes first and second source control signal generator means each for generating one of said first and second source control signals, each said first and second source control signal generator means including decoder means for receiving respective micro-control signals and for generating, in response thereto, respective first and second source control signals.

Claim 13

A processor as defined in claim 9 wherein each of said first and second source control signal generator means includes a decoder for receiving said micro-control signals and generating, in response thereto, first and second source control signals and a latch connected to said respective decoder for latching the first and second source control signals.

Claim 14

A processor as defined in claim 10 further including a plurality of registers, said control means further including counter means having a plurality of states each identifying one of said registers, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals.

Claim 15

A processor for use in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including: A. a plurality of source data means, including a plurality of registers, for providing source data signals, B. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; C. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; D. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; E. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and F. control means including: i. counter means having a plurality of states each identifying one of said registers, ii. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals, said first and second source control means each including a decoder for receiving said micro-control signals and generating, in response thereto, said first and second source control signals and a latch connected to said respective decoder for latching the first and second source control signals, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals; and iii. destination control means comprising a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for selecting one of said first source control signals or said second source control signals and coupling the selected source control signals to said output means as said destination control signals to cause said destination data selection means to transfer said processed data signals to the source data means identified by said selected one of said first source control signals of said second source control signals.

Claim 16

A processor for use in a digital data processing system, said processor performing processing operations on source data signals to provide processed data signals in response to micro-control signals, said processor including: A. a plurality of source data means, including a plurality of registers, for providing source data signals, B. arithmetic and logic means including first input terminal means, second input terminal means, output terminal means and processing means for performing selected operations on data signals at its first and second input terminal means to generate processed data signals at its output terminal means; C. first source data selection means connected to said source data means and to said first input terminal means for transferring source data signals from a first one of said source data means to said first input terminal means in response to first source control signals that identify said first source data means; D. second source data selection means connected to said source data means and to said second input terminal means for transferring source data signals from a second one of said source data means to said second input terminal means in response to second source control signals that identify said second source data means; E. destination data selection means connected to each of said source data means and to said output terminal means for transferring processed data signals to a selected one of said source data means in response to destination control signals; and F. control means including: i. counter means having a plurality of states each identifying one of said registers, ii. source control means connected to said source data selection means for generating said first source control signals and said second source control signals in response to said micro-control signals, said first and second source control means each including a decoder for receiving said micro-control signals and generating, in response thereto, said first and second source control signals and a latch connected to said respective decoder for latching the first and second source control signals, each of said first and second source control generator means further including energizable driver means for coupling the output of said counter means, as first or second source control signals, to said respective latch, said respective decoder generating an enabling signal to energize said driver means in response to selected micro-control signals; and iii. destination control means comprising a multiplexer including a first input means for receiving said first source control signals, a second input means for receiving said second source control signals, an output means for transmitting destination control signals, and a selection means responsive to said micro-control signals for selecting one of said first source control signals or said second source control signals and coupling the selected source control signals to said output means as said destination control signals to cause said destination data selection means to transfer said processed data signals to the source data means identified by said selected one of said first source control signals of said second source control signals.