Multifunction high performance graphics rendering processor

Claim 2

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; said graphics display including a bit mapped memory; block texturing and complex clip mask processor means for generating block texture signal sets and complex clip mask signal sets; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including a conics and area fill generating means for generating signal sets for the generation of open and filled conic graphics; a symbol and text generator means for generating alpha-numeric graphic symbols; a bit block transfer operator means for transferring rectangular blocks of data between the display memory and the bit mapped memory of the graphics display; a multiprocess scheduler for synchronously controlling the operation of the transfer operator means, and the block texturing and complex clip mask processor means; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween.

Claim 3

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor, said interface means including two operating channels, one of the channels having a higher operating priority than the other channel, and wherein the channels operate in parallel; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator, said display memory means including a tri-ported memory having input ports connected to the host processor, the interface means, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the processor means for controlling the input and output data, program instructions, and the plurality of parallel graphic signal sets therebetween, said display list processor means including a display memory interface unit coupled between the host processor, the graphics generator, the interface means, and the display memory means; and a readback multiplexer means operatively coupled between the display memory interface unit and a bit mapped memory of the graphics display for transferring data therebetween.

Claim 4

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor, said interface means including two operating channels, one of the channels having a higher operating priority than the other channel, and wherein the channels operate in parallel; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator, said display memory means including a tri-ported memory having input ports connected to the host processor, the interface means, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the processor means for controlling the input and output data, program instructions, and the plurality of parallel graphic signal sets therebetween, said display list processor means including a display memory interface unit coupled between the host processor, the graphics generator, the interface means, and the display memory means; and a readback multiplexer means operatively coupled between the display memory interface unit and a bit mapped memory of the graphics display for transferring data therebetween.

Claim 5

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including two hardware channels with high and low priority, the high priority channel adapted to interrupt operation of the low priority channel and process instructions immediately; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween; and context switching means adapted to save a current operational state of the graphics generator, alter the state of the graphics generator, perform a completely independent task, and then restore a previous operating state.

Claim 6

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including two hardware channels with high and low priority, the high priority channel adapted to interrupt operation of the low priority channel and process instructions immediately; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween; and context switching means adapted to save a current operational state of the graphics generator, alter the state of the graphics generator, perform a completely independent task, and then restore a previous operating state.

Claim 7

The graphics processor of claim 3 wherein nested context switching is accomplished by storing and retrieving a multitude of attribute context register values stored in an attribute stack located in the display memory.

Claim 8

The graphics processor of claim 3 that is adapted to perform both general purpose and graphics primitive processing derived from a display list stored in the display memory.

Claim 9

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; said graphics display including a bit mapped memory; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including a conics and area fill generating means for generating signal sets for the generation of open and filled conic graphics; a symbol and text generator means for generating alpha-numeric graphic symbols; a bit block transfer operator means for transferring rectangular blocks of data between the display memory and the bit mapped memory of the graphics display; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween; and wherein said bit block transfer operator means is adapted to perform a complete bit block transfer operation between a plurality of source and destination locations and wherein the plurality of source and destination locations includes bit map memory to bit map memory, display memory to bit map memory, bit map memory to display memory, host processor to display memory, display memory to host processor, host processor to bit map memory, and bit map memory to host processor.

Claim 10

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; said graphics display including a bit mapped memory; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including a conics and area fill generating means for generating signal sets for the generation of open and filled conic graphics; a symbol and text generator means for generating alpha-numeric graphic symbols; a bit block transfer operator means for transferring rectangular blocks of data between the display memory and the bit mapped memory of the graphics display; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween; and wherein said bit block transfer operator means is adapted to perform a complete bit block transfer operation between a plurality of source and destination locations and wherein the plurality of source and destination locations includes bit map memory to bit map memory, display memory to bit map memory, bit map memory to display memory, host processor to display memory, display memory to host processor, host processor to bit map memory, and bit map memory to host processor.

Claim 11

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; said graphics display including a bit mapped memory; block texturing and complex clip mask processor means for generating block texture signal sets and complex clip mask signal sets; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including a conics and are fill generating means for generating signal sets for the generation of open and filled conic graphics; a symbol and text generator means for generating alpha-numeric graphic symbols; a bit block transfer operator means for transferring rectangular blocks of data between the display memory and the bit mapped memory of the graphics display; and a multiprocess scheduler adapted to control concurrent processes in the graphics generator to allow for simultaneous concurrent operation of the primitive generators comprising the graphics generator and block texturing and complex clipping operations of the block texturing and complex clip mask processor means; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween.

Claim 12

A multifunction parallel graphics processor for use with a host processor and a graphics display, said multifunction parallel graphics processor comprising: interface means for receiving input data and program instructions from the host processor; said graphics display including a bit mapped memory; block texturing and complex clip mask processor means for generating block texture signal sets and complex clip mask signal sets; a graphics generator comprising a plurality of parallel graphics processors for generating a plurality of parallel graphic signal sets, said graphics generator including a conics and are fill generating means for generating signal sets for the generation of open and filled conic graphics; a symbol and text generator means for generating alpha-numeric graphic symbols; a bit block transfer operator means for transferring rectangular blocks of data between the display memory and the bit mapped memory of the graphics display; and a multiprocess scheduler adapted to control concurrent processes in the graphics generator to allow for simultaneous concurrent operation of the primitive generators comprising the graphics generator and block texturing and complex clipping operations of the block texturing and complex clip mask processor means; display memory means for receiving and storing the input data and program instructions from the interface means, the host processor, and the graphics generator; context register means coupled to said display memory means for receiving and storing programmable processor attribute signals that determine the graphics generator operating characteristics; and display list processor means coupled to the interface means, the display memory, and the graphics generator for controlling the input and output of data, program instructions, and the plurality of parallel graphic signal sets therebetween.