Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength

Claim 1

A method of manufacturing a MIS type semiconductor device comprising an insulating layer formed on a single crystal silicon layer surface, and an electrode layer formed on the surface of said insulating layer and for applying a predetermined voltage between said single crystal silicon layer and itself, comprising the steps of: forming a single crystal silicon layer on a substrate, a surface of the single crystal silicon layer having a surface undulation on the order of 500 Å; forming an insulating layer comprising a silicon oxide film having a thickness of 200 Å or less, using a chemical vapor deposition method, on said surface of the single crystal silicon layer; and forming an electrode layer on the surface of said insulating layer.

Claim 2

A method of manufacturing a MIS type semiconductor device comprising an insulating layer formed on a single crystal silicon layer surface, and an electrode layer formed on the surface of said insulating layer and for applying a predetermined voltage between said single crystal silicon layer and itself, comprising the steps of: forming a single crystal silicon layer on a substrate, a surface of the single crystal silicon layer having a surface undulation on the order of 500 Å; forming an insulating layer comprising a silicon oxide film having a thickness of 200 Å or less, using a chemical vapor deposition method, on said surface of the single crystal silicon layer; and forming an electrode layer on the surface of said insulating layer.

Claim 3

A method of manufacturing a field effect semiconductor device comprising an conductive layer on a surface of a source/drain region, comprising the steps of: forming a single crystal silicon layer having a surface undulation on the order of 500 Å, forming a polycrystal silicon layer and a first insulating layer on the surface of said single crystal silicon layer, exposing a surface region of the surface of said single crystal silicon layer by selectively etching and removing said polycrystal silicon layer and said first insulating layer, forming a second insulating layer comprising a silicon oxide layer having a thickness not more than 200 Å using a chemical vapor deposition method on the side of said polycrystal silicon layer, on the surface of said exposed single crystal silicon layer and on the surface of said first insulating layer, forming a gate electrode by, after forming a conductive layer on the surface of said second insulating layer, patterning it into a shape, introducing impurity into said polycrystal silicon layer, and diffusing the impurity introduced into said polycrystal silicon layer into said single crystal silicon layer.

Claim 4

A method of manufacturing a field effect semiconductor device comprising an conductive layer on a surface of a source/drain region, comprising the steps of: forming a single crystal silicon layer having a surface undulation on the order of 500 Å, forming a polycrystal silicon layer and a first insulating layer on the surface of said single crystal silicon layer, exposing a surface region of the surface of said single crystal silicon layer by selectively etching and removing said polycrystal silicon layer and said first insulating layer, forming a second insulating layer comprising a silicon oxide layer having a thickness not more than 200 Å using a chemical vapor deposition method on the side of said polycrystal silicon layer, on the surface of said exposed single crystal silicon layer and on the surface of said first insulating layer, forming a gate electrode by, after forming a conductive layer on the surface of said second insulating layer, patterning it into a shape, introducing impurity into said polycrystal silicon layer, and diffusing the impurity introduced into said polycrystal silicon layer into said single crystal silicon layer.