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US5274628A
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Multisignal synchronizer with shared last stage
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-04-24
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Granted: 1993-12-28
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Expires: 2012-04-24
Abstract
Abstract A N-stage synchronizer for generating a synchronous signal that is derived from multiple sources. The synchronizer has an edge detector and N-1 stages for each asynchronous source signal. The outputs of the N-1 the synchronizer stages are processed according to an OR function. After the OR function, the merged asynchronous source signals are input to the shared last synchronizer stage. The output of the last synchronizer stage is the synchronous signal. The N-stage synchronizer reduces capacitance associated with the synchronizer and, therefore, lessens the time to assert or de-assert the synchronous signal, and reduces the time necessary to generate the synchronous signal.
Inventors
- 👤 Kurt M. Thaller
- 👤 Nitin D. Godiwala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:46
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L5/00; H04L5/22; H04L5/24
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
170 words
A N-stage synchronizer for generating a synchronous signal that is derived from a plurality of asynchronous signals, where N≧2, N is a positive integer comprising: at least one first synchronizer stage for each of the plurality of asynchronous signals, the at least one first synchronizer stage for receiving the asynchronous signal input thereto and for outputting a first signal according to a time domain of the synchronous signal being generated; logic gate that receives as inputs the first signal from the at least one first synchronizer stage corresponding to each of the plurality of asynchronous signals, the logic gate also for outputting a second signal; at least one second synchronizer stage for receiving the second signal according to the time domain of the synchronous signal being generated; and a clock signal in the time domain of the synchronous signal being generated for controlling the timing of the at least one first and at least one second synchronizer stages wherein the at least one second synchronizer stage outputs the synchronous signal.
Claim 2
Dependent Claim
170 words
A N-stage synchronizer for generating a synchronous signal that is derived from a plurality of asynchronous signals, where N≧2, N is a positive integer comprising: at least one first synchronizer stage for each of the plurality of asynchronous signals, the at least one first synchronizer stage for receiving the asynchronous signal input thereto and for outputting a first signal according to a time domain of the synchronous signal being generated; logic gate that receives as inputs the first signal from the at least one first synchronizer stage corresponding to each of the plurality of asynchronous signals, the logic gate also for outputting a second signal; at least one second synchronizer stage for receiving the second signal according to the time domain of the synchronous signal being generated; and a clock signal in the time domain of the synchronous signal being generated for controlling the timing of the at least one first and at least one second synchronizer stages wherein the at least one second synchronizer stage outputs the synchronous signal.
Claim 3
Dependent Claim
21 words
The N-stage synchronizer as recited in claim 1, wherein each of said at least one first synchronizer stage includes a flip-flop.
Claim 4
Dependent Claim
15 words
The N-stage synchronizer as recited in claim 2, wherein the flip-flop includes a D-type flip-flop.
Claim 5
Dependent Claim
16 words
The N-stage synchronizer as recited in claim 1, wherein the logic gate is an OR gate.
Claim 6
Dependent Claim
21 words
The N-stage synchronizer as recited in claim 1, wherein each of said at least one second synchronizer stage includes a flip-flop.
Claim 7
Dependent Claim
15 words
The N-stage synchronizer as recited in claim 5, wherein the flip-flop includes a D-type flip-flop.
Claim 8
Dependent Claim
59 words
The N-stage synchronizer as recited in claim 1, further comprising a plurality of edge detectors, each one of the plurality of edge detectors receiving as an input one of the plurality of asynchronous signals, each one of the plurality of edge detectors also having an output coupled to a corresponding one of the at least one first synchronizer stages.
Claim 9
Dependent Claim
15 words
The N-stage synchronizer as recited in claim 7, wherein each edge detector includes a flip-flop.
Claim 10
Dependent Claim
158 words
A N-stage synchronizer for generating a synchronous signal that is derived from a plurality of asynchronous signals, where N≧2, N is a positive integer, comprising: a set of N-1 synchronizer stages for each of the plurality of asynchronous signals, each set of N-1 synchronizer stage for receiving one of the plurality of asynchronous signals input thereto and for outputting a first signal according to a time domain of the synchronous signal being generated: logic gate that receives as inputs the first signal from each set of N-1 synchronizer stages corresponding to the plurality of asynchronous signals, the logic gate also for outputting a second signal; Nth synchronizer stage for receiving the second signal according to the time domain of the synchronous signal being generated; and a clock signal in the time domain of the synchronous signal being generated, the clock signal for controlling timing of the N synchronizer stages wherein the Nth synchronizer stage outputs the synchronous signal.
Claim 11
Dependent Claim
158 words
A N-stage synchronizer for generating a synchronous signal that is derived from a plurality of asynchronous signals, where N≧2, N is a positive integer, comprising: a set of N-1 synchronizer stages for each of the plurality of asynchronous signals, each set of N-1 synchronizer stage for receiving one of the plurality of asynchronous signals input thereto and for outputting a first signal according to a time domain of the synchronous signal being generated: logic gate that receives as inputs the first signal from each set of N-1 synchronizer stages corresponding to the plurality of asynchronous signals, the logic gate also for outputting a second signal; Nth synchronizer stage for receiving the second signal according to the time domain of the synchronous signal being generated; and a clock signal in the time domain of the synchronous signal being generated, the clock signal for controlling timing of the N synchronizer stages wherein the Nth synchronizer stage outputs the synchronous signal.
Claim 12
Dependent Claim
18 words
The N-stage synchronizer as recited in claim 9, wherein each of the N synchronizer stages includes a flip-flop.
Claim 13
Dependent Claim
15 words
The N-stage synchronizer as recited in claim 10, wherein the flip-flop includes a D-type flip-flop.
Claim 14
Dependent Claim
16 words
The N-stage synchronizer as recited in claim 9, wherein the logic gate includes an OR gate.
Claim 15
Dependent Claim
57 words
The N-stage synchronizer as recited in claim 9, further comprising a plurality of edge detectors, each one of the plurality of edge detectors receiving as input one of the plurality of asynchronous signals, each one of the plurality of edge detectors having an output coupled to a particular stage of the corresponding set of N-1 synchronizer stages.
Claim 16
Dependent Claim
15 words
The N-stage synchronizer as recited in claim 13, wherein each edge detector includes a flip-flop.
Claim 17
Independent Claim
139 words
A method for generating a synchronous signal from a plurality of asynchronous signals, comprising the steps of: transmitting each asynchronous signal to a respective set of N-1 synchronization stages, where N≧2, N is a positive integer, the timing for each of the respective sets of N-1 synchronization stages being in a time domain of the synchronous signal being generated, each one of the respective N-1 synchronization stages producing an output; inputting to a logic gate the outputs of the respective sets of N-1 synchronization stages, with the logic gate producing a logic gate output; and inputting the logic gate output to an Nth synchronization signal stage, the timing for the Nth synchronization signal stage being in the time domain of the synchronous signal being generated, and generating the synchronous signal at the output of the Nth synchronization signal stage.
Claim 18
Independent Claim
139 words
A method for generating a synchronous signal from a plurality of asynchronous signals, comprising the steps of: transmitting each asynchronous signal to a respective set of N-1 synchronization stages, where N≧2, N is a positive integer, the timing for each of the respective sets of N-1 synchronization stages being in a time domain of the synchronous signal being generated, each one of the respective N-1 synchronization stages producing an output; inputting to a logic gate the outputs of the respective sets of N-1 synchronization stages, with the logic gate producing a logic gate output; and inputting the logic gate output to an Nth synchronization signal stage, the timing for the Nth synchronization signal stage being in the time domain of the synchronous signal being generated, and generating the synchronous signal at the output of the Nth synchronization signal stage.
Claim 19
Dependent Claim
17 words
The method as recited in claim 15, wherein each of the N synchronization stages includes a flip-flop.
Claim 20
Dependent Claim
18 words
The method as recited in claim 16, wherein each of the N synchronization stages includes a D-type flip-flop.
Claim 21
Dependent Claim
15 words
The method as recited in claim 15, wherein the logic gate includes an or gate.
Claim 22
Independent Claim
134 words
A method for generating a synchronous signal from a plurality of asynchronous signals, comprising the steps of: operating at least one first synchronization stage to receive each one of the plurality of asynchronous signals and to output a respective first signal therefrom, the timing for each of the at least one first synchronization stage being in a time domain of the synchronous signal being generated; inputting to a logic gate the respective first signal of each of the at least one first synchronization stages, the logic gate producing a second signal at its output; and operating at least one second synchronization stage to receive the second signal and to generate the synchronization signal, the timing for the at least one second synchronization stage being in the time domain of the synchronous signal being generated.
Claim 23
Independent Claim
134 words
A method for generating a synchronous signal from a plurality of asynchronous signals, comprising the steps of: operating at least one first synchronization stage to receive each one of the plurality of asynchronous signals and to output a respective first signal therefrom, the timing for each of the at least one first synchronization stage being in a time domain of the synchronous signal being generated; inputting to a logic gate the respective first signal of each of the at least one first synchronization stages, the logic gate producing a second signal at its output; and operating at least one second synchronization stage to receive the second signal and to generate the synchronization signal, the timing for the at least one second synchronization stage being in the time domain of the synchronous signal being generated.
Claim 24
Dependent Claim
23 words
The method as recited in claim 19, wherein the step of operating the at least one first synchronization stage includes operating a flip-flop.
Claim 25
Dependent Claim
24 words
The method as recited in claim 20, wherein the step of operating the at least one first synchronization stage includes operating a D-type flip-flop.
Claim 26
Dependent Claim
23 words
The method as recited in claim 19, wherein the step of operating the at least one second synchronization stage includes operating a flip-flop.
Claim 27
Dependent Claim
24 words
The method as recited in claim 22, wherein the step of operating the at least one second synchronization stage includes operating a D-type flip-flop.
Claim 28
Dependent Claim
15 words
The method as recited in claim 19, wherein the logic gate includes an OR gate.
Claim 29
Dependent Claim
29 words
The method as recited in claim 19, wherein the method further comprises the step of using an edge detector before each of the at least one first synchronization stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-27 | 1997-06-28 | 1997-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-27 | 2001-06-28 | 2001-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-27 | 2005-06-28 | 2005-12-28 | $7700.00 | Window Closed / Lapsed |