Semiconductor device having a capacitor dielectric film of multilayer structure and a method of controlling the same

Claim 2

A semiconductor device comprising: a storage capacitor for storing a high logic level voltage VH and a low logic level voltage VL of a logic signal, said storage capacitor having first and second plates separated by a multilayer dielectric film, said first plate connected for receiving at said first plate said logic signal having said high and low logic level voltages, and a fixed potential generator connected to said second plate for applying to said second plate a fixed voltage VGG greater than zero and less than an arithmetic average of VL and VH, wherein VGG is within a voltage range expressed by: 0.65 (VH-VL) -1.3≧VGG≧0.65 (VH-VL) -2.5.

Claim 3

The semiconductor device according to claim 1, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.75 to 1.95 volts, and said high logic level voltage VH is nominally 5 volts.

Claim 4

The semiconductor device according to claim 2, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.9 to 1.3 volts and said high logic level voltage VH is nominally 5 volts.

Claim 5

The semiconductor device according to claim 1, wherein said multilayer dielectric film comprises a silicon nitride film formed on said first plate and a silicon oxide film covering said silicon nitride film on a side opposite said first plate.

Claim 10

The semiconductor device according to claim 6, wherein said low logic level voltage VL is nominally zero volts, said fixed voltage is nominally within a range of 0.75 to 1.95 volts, and said high logic level signal VH is nominally 5 volts.

Claim 11

The semiconductor device according to claim 7, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.9 to 1.3 volts and said high logic level voltage VH is nominally 5 volts.

Claim 12

The semiconductor device according to claim 6, wherein said multilayer dielectric film comprises a silicon nitride film formed on said first plate and a silicon oxide film covering said silicon nitride film on a side opposite said first plate.

Claim 15

65 (VH-VL) -1.3≧VGG≧0.65 (VH-VL) -2.5.

Claim 16

65 (VH-VL) -1.3≧VGG≧0.65 (VH-VL) -2.5.

Claim 17

The semiconductor device according to claim 10, wherein said low logic level voltage VL is nominally zero volts, said fixed voltage is nominally within a range of 0.75 to 1.95 volts, and said high logic level voltage VH is nominally 5 volts.

Claim 18

The semiconductor device according to claim 11, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.9 to 1.3 volts and said high logic level voltage VH is nominally 5 volts.

Claim 19

The semiconductor device according to claim 10, wherein said multilayer dielectric film comprises a silicon nitride film formed on said first plate and a silicon oxide film covering said silicon nitride film on a side opposite said first plate.

Claim 20

A semiconductor device comprising: a storage capacitor for storing a high logic level voltage VH and a low logic level voltage VL of a logic signal, said storage capacitor having first and second plates separated by a multilayer dielectric film, said first plate connected for receiving at said first plate said logic signal having said high and low logic level voltages, and a fixed potential generator connected to said second plate for applying to said second plate a fixed voltage VGG greater than zero and less than an arithmetic average of VL and VH, wherein said first and second plates are formed of the same material.

Claim 21

A semiconductor device comprising: a storage capacitor for storing a high logic level voltage VH and a low logic level voltage VL of a logic signal, said storage capacitor having first and second plates separated by a multilayer dielectric film, said first plate connected for receiving at said first plate said logic signal having said high and low logic level voltages, and a fixed potential generator connected to said second plate for applying to said second plate a fixed voltage VGG greater than zero and less than an arithmetic average of VL and VH, wherein said first and second plates are formed of the same material.

Claim 22

In a method of controlling a semiconductor device comprising a capacitor having first and second electrodes separated by a multilayer dielectric film, wherein said first and second electrodes are formed of the same material, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying high and low voltages VH and VL alternately to said first electrode at the time of operation, and applying a fixed voltage VGG greater than zero and less than an arithmetic average of said high voltage VH and said low voltage VL to said second electrode.

Claim 23

In a method of controlling a semiconductor device comprising a capacitor having first and second electrodes separated by a multilayer dielectric film, wherein said first and second electrodes are formed of the same material, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying high and low voltages VH and VL alternately to said first electrode at the time of operation, and applying a fixed voltage VGG greater than zero and less than an arithmetic average of said high voltage VH and said low voltage VL to said second electrode.

Claim 24

In a method of selectively storing a high logic level signal VH and a low logic level signal VL in a storage capacitor having first and second plates separated by a multilayer dielectric film, wherein said first and second plates are formed of the same material, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying a fixed voltage VGG to said second plate, and applying selectively said high logic level signal VH and said low logic level signal VL to said first plate wherein VGG is greater than zero and less than an arithmetic average of VL and VH, whereby corresponding charges are stored in said capacitor respectively representing high and low logic level signals.

Claim 25

In a method of selectively storing a high logic level signal VH and a low logic level signal VL in a storage capacitor having first and second plates separated by a multilayer dielectric film, wherein said first and second plates are formed of the same material, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying a fixed voltage VGG to said second plate, and applying selectively said high logic level signal VH and said low logic level signal VL to said first plate wherein VGG is greater than zero and less than an arithmetic average of VL and VH, whereby corresponding charges are stored in said capacitor respectively representing high and low logic level signals.

Claim 26

In a method of operating a semiconductor device, said device including a plurality of word lines, a plurality of bit lines arranged crossing said word lines forming a matrix, and a plurality of memory cells arranged at crossings of the word lines and the bit lines, each of said memory cells including a storage capacitor for storing a high logic level voltage VH and a low logic level voltage VL, said storage capacitor having first and second plates separated by a multilayer dielectric film, wherein said first and second plates are formed of the same material, said first plate connected to a second switched terminal of said semiconductor switching element for receiving at said first plate a logic signal having said high and low logic level voltages, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying a non-zero fixed voltage VGG to said second plate which is less than an arithmetic average of said high and low logic level voltages VH and VL, selectively applying one of said high logic level voltage VH and said low logic level voltage VL to one of said bit lines, applying a row selecting voltage to one of said word lines, and in response to said row selecting voltage, connecting a respective capacitor of one of said memory cells to said respective one of said bit lines for receiving said selectively applied one of said high and low logic level voltages VH and VL.

Claim 27

In a method of operating a semiconductor device, said device including a plurality of word lines, a plurality of bit lines arranged crossing said word lines forming a matrix, and a plurality of memory cells arranged at crossings of the word lines and the bit lines, each of said memory cells including a storage capacitor for storing a high logic level voltage VH and a low logic level voltage VL, said storage capacitor having first and second plates separated by a multilayer dielectric film, wherein said first and second plates are formed of the same material, said first plate connected to a second switched terminal of said semiconductor switching element for receiving at said first plate a logic signal having said high and low logic level voltages, the improvement comprising increasing reliability of the multilayer dielectric film by performing the steps of: applying a non-zero fixed voltage VGG to said second plate which is less than an arithmetic average of said high and low logic level voltages VH and VL, selectively applying one of said high logic level voltage VH and said low logic level voltage VL to one of said bit lines, applying a row selecting voltage to one of said word lines, and in response to said row selecting voltage, connecting a respective capacitor of one of said memory cells to said respective one of said bit lines for receiving said selectively applied one of said high and low logic level voltages VH and VL.

Claim 28

The semiconductor device according to claim 14, wherein VGG is within a voltage range expressed by: 0.65 (VH-VL) -1.3≧VGG≧0.65 (VH-VL) -2.5.

Claim 29

The semiconductor device according to claim 14, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.75 to 1.95 volts, and said high logic level voltage VH is nominally 5 volts.

Claim 30

The semiconductor device according to claim 1, further comprising: a plurality of said storage capacitors; a plurality of word lines; a plurality of bit lines crossing said word lines forming a matrix; a plurality of memory cells arranged at crossings of the word lines and the bit lines, each of said memory cells including (i) a semiconductor switching element responsive to a selection signal for selecting one of said memory cells having a first switched terminal connected to one of said bit lines and a control terminal connected to one of said word lines, and (ii) one of said plurality of storage capacitors having a respective one of said first plates connected to a second switched terminal of said semiconductor switching element for receiving said logic signal at said respective first plate thereof.

Claim 31

The semiconductor device according to claim 20, wherein said low logic level voltage VL is nominally zero volts, said fixed voltage is nominally within a range of 0.75 to 1.95 volts, and said high logic level voltage VH is nominally 5 volts.

Claim 32

The semiconductor device according to claim 21, wherein said low logic level voltage is nominally zero volts, said fixed voltage is nominally within a range of 0.9 to 1.3 volts and said high logic level voltage VH is nominally 5 volts.

Claim 33

The semiconductor device according to claim 20, wherein said multilayer dielectric film comprises a silicon nitride film formed on said first plate and a silicon oxide film covering said silicon nitride film on a side opposite said first plate.