High speed "OR" circuit configuration

Claim 2

A circuit comprising: an output node; a first plurality of MOS logic circuits, each of said first plurality of MOS logic circuits generating a first output capable of being at a first or second logic state; a plurality of bipolar transistor circuit means coupled to and responsive to the outputs of said first plurality of MOS logic circuits, said plurality of bipolar transistor circuit means coupled in a WIRED-OR configuration to said output node and for transitioning said output node to the first state if at least one of said first plurality is in the first state; a second plurality of MOS logic circuits, each of said second plurality of MOS logic having a second output capable of being at a first or second state, wherein each of the second plurality of MOS logic circuits is a skewed version of each of said first plurality of MOS logic circuits, such that the transition of each second output from the first state to the second state is faster than the transition from the second state to the first state; ORing means coupled to receive the second outputs from said second plurality, wherein the ORing means has a third output coupled to the output node, such that if all of said second outputs are in the second state then the output node is in said second state; wherein the transition of the output node from the second state to the first state is provided by said first plurality of MOS logic circuits and said plurality of bipolar transistor circuit means and the transition of the output from the first state to the second state is provided by the second plurality of MOS logic circuits and said ORing means.

Claim 3

The circuit as defined in claim 1 wherein the first and second plurality of MOS logic circuits comprise complementary MOS (CMOS) logic.

Claim 4

The circuit as defined in claim 1 wherein said ORing means includes: at least one NORing means coupled to the outputs of said second plurality, each of said at least one NORing means for providing an intermediate output indicative of a NORing function in response to the outputs of said second plurality, wherein said intermediate output is capable of being at a first or second state and is skewed, such that the transition of the intermediate output from the second state to the first state is faster than the transition from the first state to the second state; and second circuit means coupled to receive the intermediate outputs from said at least one NORing means and putting the output node in the second state, wherein said second circuit means is skewed, such that the transition of the output node from the first state to the second state is faster than the transition from the second state to the first state.

Claim 5

The circuit as defined in claim 3 wherein the at least one NORing means comprises at least one NOR gate.

Claim 6

The circuit as defined in claim 3 wherein said second circuit means comprises a transistor stack having at least one transistor device.

Claim 7

The circuit as defined in claim 5 wherein each transistor in said transistor stack comprises an n-channel transistor.

Claim 8

The circuit as defined in claim 1 wherein each of said plurality of bipolar transistor circuit means includes a protection mechanism.

Claim 9

The circuit as defined in claim 7 wherein said protection mechanism comprises a bipolar device.

Claim 10

The circuit as defined in claim 7 wherein said protection mechanism comprises a diode.

Claim 11

A circuit for providing an OR function on the outputs of at least two MOS logic circuits comprising: an output node capable of being in a first or second logic state and being responsive to a first or second path; a first path including a plurality of WIRED-OR means responsive to the outputs of said at least two MOS logic circuits, such that if at least one of said MOS logic circuits is in the first state then the first path transitions the output node into the first state; a second path including a skewed version of each of said at least two MOS logic circuits, wherein said at least two MOS logic circuits are skewed for the second state, such that the second path is capable of transitioning the output node from the first state to the second state faster than transitioning the output node from the second state to the first state; wherein the transition of the output node from the first state to the second state is provided by said second path and the transition of the output node from the second state to the first state is provided by said first path.

Claim 12

A circuit for providing an OR function on the outputs of at least two MOS logic circuits comprising: an output node capable of being in a first or second logic state and being responsive to a first or second path; a first path including a plurality of WIRED-OR means responsive to the outputs of said at least two MOS logic circuits, such that if at least one of said MOS logic circuits is in the first state then the first path transitions the output node into the first state; a second path including a skewed version of each of said at least two MOS logic circuits, wherein said at least two MOS logic circuits are skewed for the second state, such that the second path is capable of transitioning the output node from the first state to the second state faster than transitioning the output node from the second state to the first state; wherein the transition of the output node from the first state to the second state is provided by said second path and the transition of the output node from the second state to the first state is provided by said first path.

Claim 13

A comparator for use in performing a tag matching operation between the address of a memory request and the tag address in a cache for a microprocessor comprising: an output node; a plurality of exclusive-NOR gate means for receiving the address of the memory request and the tag address and performing the exclusive-NOR function on corresponding bit locations of the two addresses, each of said plurality of exclusive-OR gate means producing a first output; a first plurality of NAND gate means, wherein each of said NAND gate means generates a second output capable of being at a first or second logic state as a result of performing a NAND function on the first outputs of said plurality of exclusive-OR gate means; a plurality of bipolar circuit means coupled to and responsive to the outputs of said first plurality of NAND, said plurality of bipolar transistor circuit means coupled in a WIRED-OR configuration to said output node and for transitioning said output node to the first state if at least one of said first plurality is in the first state; a second plurality of MOS NAND gate means, each of said second plurality having a third output capable of being at a first or second logic state, wherein each of the second plurality is a skewed version of each of said first plurality, such that the transition of the third output from the first state to the second state is faster than the transition from the second state to the first state; ORing means coupled to recieve the third outputs from said second plurality, wherein said ORing means produces a fourth output coupled to the output node, such that if the third output of at least one of said second plurality of MOS NAND gate means is in the second state then the output is put in the second state and; wherein the transition of the output node from the second state to the first state is provided by said second plurality and said ORing means and the transition of the output node from the first state to the second state is provided by the first plurality and the plurality of bipolar circuit means, such that if said output node is in said first state then the comparator indicates that a match occurred and if said output node is in said second state then the said comparator indicates that a match did not occur.

Claim 14

A comparator for use in performing a tag matching operation between the address of a memory request and the tag address in a cache for a microprocessor comprising: an output node; a plurality of exclusive-NOR gate means for receiving the address of the memory request and the tag address and performing the exclusive-NOR function on corresponding bit locations of the two addresses, each of said plurality of exclusive-OR gate means producing a first output; a first plurality of NAND gate means, wherein each of said NAND gate means generates a second output capable of being at a first or second logic state as a result of performing a NAND function on the first outputs of said plurality of exclusive-OR gate means; a plurality of bipolar circuit means coupled to and responsive to the outputs of said first plurality of NAND, said plurality of bipolar transistor circuit means coupled in a WIRED-OR configuration to said output node and for transitioning said output node to the first state if at least one of said first plurality is in the first state; a second plurality of MOS NAND gate means, each of said second plurality having a third output capable of being at a first or second logic state, wherein each of the second plurality is a skewed version of each of said first plurality, such that the transition of the third output from the first state to the second state is faster than the transition from the second state to the first state; ORing means coupled to recieve the third outputs from said second plurality, wherein said ORing means produces a fourth output coupled to the output node, such that if the third output of at least one of said second plurality of MOS NAND gate means is in the second state then the output is put in the second state and; wherein the transition of the output node from the second state to the first state is provided by said second plurality and said ORing means and the transition of the output node from the first state to the second state is provided by the first plurality and the plurality of bipolar circuit means, such that if said output node is in said first state then the comparator indicates that a match occurred and if said output node is in said second state then the said comparator indicates that a match did not occur.