US5270983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single element security fusible link
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1990-09-13
•
Granted: 1993-12-14
•
Expires: 2010-09-13
Abstract
Abstract An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.
Inventors
- 👤 William J. Wuertz
- 👤 Steven K. Stefek
- 👤 William W. McKinley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:19
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
75 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; and a diode connected between said signal line and second pad; wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse, and wherein said signal line is a write enable line connected to a RAM.
Claim 2
Dependent Claim
75 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; and a diode connected between said signal line and second pad; wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse, and wherein said signal line is a write enable line connected to a RAM.
Claim 3
Dependent Claim
73 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a diode connected between said signal line and second pad; and a resistor connected between said signal line and a reference voltage terminal, wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse.
Claim 4
Dependent Claim
73 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a diode connected between said signal line and second pad; and a resistor connected between said signal line and a reference voltage terminal, wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse.
Claim 5
Dependent Claim
12 words
The circuit of claim 2 wherein said reference voltage terminal is ground.
Claim 6
Dependent Claim
19 words
The circuit of claim 3 further comprising: an I/O line connected from said first pad to a logic circuit.
Claim 7
Dependent Claim
19 words
The circuit of claim 4 further comprising: an I/O line connected from said second pad to a logic circuit.
Claim 8
Dependent Claim
77 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; and a second diode connected from said first pad to a reference voltage terminal, wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
Claim 9
Dependent Claim
77 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; and a second diode connected from said first pad to a reference voltage terminal, wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
Claim 10
Dependent Claim
32 words
The circuit of claim 6 wherein said second diode is an N channel transistor having its control electrode connected to said reference voltage terminal, and wherein said reference voltage terminal is ground.
Claim 11
Dependent Claim
92 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; a second diode connected from said second pad to a first reference voltage terminal, and a third diode connected from said second pad to a second reference voltage terminal, wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
Claim 12
Dependent Claim
92 words
In an integrated circuit, an I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; a second diode connected from said second pad to a first reference voltage terminal, and a third diode connected from said second pad to a second reference voltage terminal, wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
Claim 13
Dependent Claim
46 words
The circuit of claim 8 wherein said second diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, and wherein said third diode is a P channel transistor having its control electrode connected to said second reference voltage terminal.
Claim 14
Dependent Claim
23 words
The circuit of claim 9 wherein said first reference voltage terminal is ground and said second reference voltage terminal is about 5 volts.
Claim 15
Dependent Claim
115 words
An I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; a resistor connected between said signal line and a first reference voltage terminal; a first I/O line connected from said first fuse pad to a logic circuit; a second I/O line connected from said second fuse pad to said logic circuit; a second diode connected from said first pad to said first reference voltage terminal; a third diode connected from said second pad to said first reference voltage terminal; and a fourth diode connected from said second pad to a second reference voltage terminal.
Claim 16
Dependent Claim
115 words
An I/O circuit comprising: first and second I/O pads; a fuse connected between said first pad and a signal line; a first diode connected between said signal line and second pad; a resistor connected between said signal line and a first reference voltage terminal; a first I/O line connected from said first fuse pad to a logic circuit; a second I/O line connected from said second fuse pad to said logic circuit; a second diode connected from said first pad to said first reference voltage terminal; a third diode connected from said second pad to said first reference voltage terminal; and a fourth diode connected from said second pad to a second reference voltage terminal.
Claim 17
Dependent Claim
23 words
The circuit of claim 11 wherein said first diode is an N channel transistor having its control electrode connected to said signal line.
Claim 18
Dependent Claim
84 words
The circuit of claim 12 wherein said second diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, wherein said third diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, wherein said fourth diode is a P channel transistor having its control electrode connected to said second reference voltage terminal, and wherein said first reference voltage terminal is ground and said second reference voltage terminal is about 5 volts.
Claim 19
Dependent Claim
12 words
The circuit of claim 13 wherein each of said transistors is MOSFET.
Claim 20
Dependent Claim
18 words
The circuit of claim 14 wherein said signal line is a write enable line connected to a RAM.
References Cited (Backward Citations)
US4157480A
Cited
US4446534A
Cited
US4417154A
Cited
US4480199A
Cited
US4903111A
Cited
US4935645A
Cited
JPH02192093A
Cited
US4933898A
Cited
JPH02189799A
Cited
US5065057A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |