Patent US5270980A successfully refreshed from Google Patents.
US5270980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sector erasable flash EEPROM
Assignee: Eastman Kodak Co
•
Filing: 1991-10-28
•
Granted: 1993-12-14
•
Expires: 2011-10-28
Abstract
Abstract A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided that applies a first erase voltage to the control gates of selected floating gate memory cells of the array to prevent erasure of the selected floating gate memory cells and a second erase voltage to the control gates of the remaining floating gate memory cells of the array to permit erasure of the remaining floating gate memory cells in a sector erase mode of operation. The decoder is also preferably capable of supplying the second erase voltage to the control gates of each of the floating gate memory cells in a bulk erase mode of operation.
Inventors
- 👤 Jagdish Pathak
- 👤 John Caywood
- 👤 Timothy J. Tredwell
- 👤 Constantine N. Anagnostopoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
234 words
A memory device comprising: a plurality of floating gate memory cells arranged in an array of rows and columns, wherein each memory cell includes a control gate, a drain and a source, and wherein the control gates of the memory cells in the rows of the area are connected to common word decode lines, the drains of the memory cells in the columns of the array are connected to common column decode lines, and the sources of all of the memory cells are commonly connected to a source voltage line; and erase decoding means, coupled to the word decode lines, for applying a first erase voltage to the control gates of a first group of said memory cells to prevent erasure of said first group of memory cells and for applying a second erase voltage to the control gates of a second group of said memory cells to permit erasure of said second group of memory cells when a source erase voltage is applied to said source voltage line in a sector erase mode of operation; wherein said first erase voltage is greater than said source erase voltage and said source erase voltage is greater than said second erase voltage, and wherein said first erase voltage is sufficient to prevent tunneling of electrons from floating gate regions of the first group of memory cells to the sources of the first group of memory cells.
Claim 2
Dependent Claim
234 words
A memory device comprising: a plurality of floating gate memory cells arranged in an array of rows and columns, wherein each memory cell includes a control gate, a drain and a source, and wherein the control gates of the memory cells in the rows of the area are connected to common word decode lines, the drains of the memory cells in the columns of the array are connected to common column decode lines, and the sources of all of the memory cells are commonly connected to a source voltage line; and erase decoding means, coupled to the word decode lines, for applying a first erase voltage to the control gates of a first group of said memory cells to prevent erasure of said first group of memory cells and for applying a second erase voltage to the control gates of a second group of said memory cells to permit erasure of said second group of memory cells when a source erase voltage is applied to said source voltage line in a sector erase mode of operation; wherein said first erase voltage is greater than said source erase voltage and said source erase voltage is greater than said second erase voltage, and wherein said first erase voltage is sufficient to prevent tunneling of electrons from floating gate regions of the first group of memory cells to the sources of the first group of memory cells.
Claim 3
Dependent Claim
52 words
A memory device as claimed in claim 1, wherein said erase decoding means includes means for applying said second erase voltage to the control gates of each of said floating gate memory cells when the source erase voltage is applied to said source voltage line in a bulk erase mode of operation.
Claim 4
Dependent Claim
26 words
A memory device as claimed in claim 2, wherein said first erase voltage is approximately 12-14 volts and said second erase voltage is approximately ground potential.
References Cited (Backward Citations)
US4931997A
Cited
US4949309A
Cited
US4996571A
Cited
US5034926A
Cited
US5172338A
Cited
US5172338B1
Cited
US5109361A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |