Process for filling submicron spaces with dielectric

Claim 2

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed at a pressure such that a substantial amount of the etched ILD material is redeposited in said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 3

The process as in claim 1, wherein said sputter etching uses argon, krypton, or xenon and said pressure is approximately 80-200 mTorr.

Claim 4

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed at a pressure such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 5

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed at a pressure such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 6

The process as in claim 3, wherein said sputter etching uses argon, krypton, or xenon and said pressure is approximately 80-200 mTorr.

Claim 7

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 8

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 9

The process as in claim 5, wherein said sputter etching uses argon, krypton, or xenon and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 10

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD, with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.

Claim 11

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD, with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.

Claim 12

The process as in claim 7, wherein said sputter etching is argon sputter etching and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 13

The process as in claim 7, wherein said widths of said gaps are less than 0.70 um, wherein said sputter etching uses krypton or xenon, and wherein said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 14

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 15

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 16

The process as in claim 10, wherein said sputter etching uses argon, krypton, or xenon and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 17

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.

Claim 18

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using PECVD such that said gaps between said metal lines are completely filled.

Claim 19

The process as in claim 12, wherein said sputter etching is argon sputter etching and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 20

The process as in claim 12, wherein said widths of said gaps are less than 0.70 um, wherein said sputter etching uses krypton or xenon, and wherein said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 21

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 22

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using chemical vapor deposition, CVD, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein said gaps are submicron-wide, wherein said gaps have aspect ratios greater than 1.0, wherein said gaps may have reentrant angles; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 23

The process as in claim 15, wherein said sputter etching uses argon, krypton, or xenon and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 24

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 25

In the field of semiconductor wafer processing, an improvement to a process for filling gaps between adjacent metal lines on a semiconductor wafer with an inter-layer dielectric, ILD, wherein said semiconductor wafer has transistors, comprising the steps of: depositing a first ILD layer using plasma enhanced chemical vapor deposition, PECVD with either TEOS or silane as the silicon source, wherein said ILD deposits preferentially on the upper edges of said metal lines to form bread-loaf edges, wherein said first ILD layer does not completely fill said gaps, wherein the widths of said gaps are less than 0.8 um, wherein the aspect ratios of said gaps are greater than 1.0, wherein said gaps may have a reentrant angle; sputter etching said first ILD layer, said sputter etching being performed using combinations of power, pressure, and magnetic field such that said first ILD layer is preferentially etched at said bread-loaf edges and the etched material is redeposited in said gaps to partially fill said gaps and such that said combinations of power, pressure, and magnetic field minimize the damage to the transistors on said wafer caused by said sputter etching, said combinations also maximizing the etch rate of said sputter etching to the extent possible without damaging the transistors, said sputter etching step following said depositing said first ILD layer step; and depositing a second ILD layer using CVD such that said gaps between said metal lines are completely filled.

Claim 26

The process as in claim 17, wherein said sputter etching is argon sputter etching and said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.

Claim 27

The process as in claim 17, wherein said widths of said gaps are less than 0.70 um, wherein said sputter etching uses krypton or xenon, and wherein said combinations of power, pressure, and magnetic field are approximately 1.9-3.0 Watts/(cm 2 of upper wafer area), approximately 80-200 mTorr, and approximately 30-60 Gauss, respectively.