Fabrication process of a semiconductor device having a reduced parasitic capacitance

Claim 1

A method for fabricating a semiconductor device, comprising the steps of: providing a temporary layer on a major surface of a semiconductor substrate; patterning the temporary layer to form a temporary pattern on the main surface of the semiconductor substrate, in correspondence to a part of said main surface on which the semiconductor device is to be formed, said step of patterning the temporary layer being conducted such that the temporary pattern has a side wall and the surface of the semiconductor substrate is exposed in a portion thereof at and adjacent said side wall; forming a conductor layer, of a material incorporating therein an impurity element, such that the conductor layer buries the temporary pattern therebeneath and is in intimate contact with said side wall of said temporary pattern and with the exposed surface portion of the semiconductor substrate adjacent the side wall of the temporary pattern; patterning the conductor layer to form a conductor region in intimate contact with the side wall of the temporary pattern and in intimate contact with the exposed surface portion of the semiconductor substrate, said step of patterning the conductor layer comprising anisotropically etching the conductor layer selectively in a direction perpendicular to the major surface of said semiconductor substrate thereby to remove said conductor layer except for a wall-like region thereof located immediately adjacent to and remaining in intimate contact with said side wall of said temporary pattern; removing the temporary pattern selectively with respect to the wall-like conductor region; and forming a diffusion region in the semiconductor substrate, in correspondence to a surface portion thereof on which said wall-like conductor region is provided, by causing a diffusion thereinto of said impurity element.

Claim 2

A method for fabricating a semiconductor device, comprising the steps of: providing a temporary layer on a major surface of a semiconductor substrate; patterning the temporary layer to form a temporary pattern on the main surface of the semiconductor substrate, in correspondence to a part of said main surface on which the semiconductor device is to be formed, said step of patterning the temporary layer being conducted such that the temporary pattern has a side wall and the surface of the semiconductor substrate is exposed in a portion thereof at and adjacent said side wall; forming a conductor layer, of a material incorporating therein an impurity element, such that the conductor layer buries the temporary pattern therebeneath and is in intimate contact with said side wall of said temporary pattern and with the exposed surface portion of the semiconductor substrate adjacent the side wall of the temporary pattern; patterning the conductor layer to form a conductor region in intimate contact with the side wall of the temporary pattern and in intimate contact with the exposed surface portion of the semiconductor substrate, said step of patterning the conductor layer comprising anisotropically etching the conductor layer selectively in a direction perpendicular to the major surface of said semiconductor substrate thereby to remove said conductor layer except for a wall-like region thereof located immediately adjacent to and remaining in intimate contact with said side wall of said temporary pattern; removing the temporary pattern selectively with respect to the wall-like conductor region; and forming a diffusion region in the semiconductor substrate, in correspondence to a surface portion thereof on which said wall-like conductor region is provided, by causing a diffusion thereinto of said impurity element.

Claim 6

A method for fabricating a semiconductor device, comprising the steps of: providing a temporary layer on a surface of a semiconductor substrate on which the semiconductor device is to be formed; patterning the temporary layer to form a temporary protection pattern on the main surface of the semiconductor substrate such that the temporary protection pattern has a pair of opposing side walls extending generally vertically to the surface of the semiconductor substrate and such that surface portions of the semiconductor substrate are exposed at and adjacent said both opposing side walls of the temporary protection pattern; forming a first conductor layer, of a material that incorporates therein an impurity element of a first conductivity type, such that the conductor layer buries the temporary protection pattern therebeneath and is in intimate contact with said both opposing side walls of the temporary protection pattern and with the exposed surface portions of the semiconductor substrate at and adjacent both said opposing side walls of the temporary protection pattern; patterning the first conductor layer to form a pair of first type conductor regions adjacent to and in intimate contact with, respectively, said both opposing side walls of the temporary protection pattern, said step of patterning the first conductor layer comprising anisotropically etching the conductor layer selectively in a direction perpendicular to the major surface of said semiconductor substrate thereby to remove said conductor layer except for said pair of first type conductor regions, respectively located immediately adjacent to and in intimate contact with said opposing side walls of said temporary protection pattern; removing the temporary protection pattern selectively with respect to said pair of first type conductor regions and such that said pair of first type conductor regions remains on, and in intimate contact with, the semiconductor layer such that each of said pair of first type conductor regions has an exposed side wall that extends generally vertically to the surface of the semiconductor substrate; forming a second conductor layer such that the second conductor layer buries said pair of first type conductor regions therebeneath; patterning the second conductor layer such that a potion of the second conductor layer remains, between said pair of first type conductor regions, as a second type conductor region; and forming first diffusion regions in the semiconductor substrate, respectively in correspondence to major surface portions thereof on which said pair of first type conductor regions are provided, by causing diffusion thereinto of said impurity element.

Claim 7

A method for fabricating a semiconductor device, comprising the steps of: providing a temporary layer on a surface of a semiconductor substrate on which the semiconductor device is to be formed; patterning the temporary layer to form a temporary protection pattern on the main surface of the semiconductor substrate such that the temporary protection pattern has a pair of opposing side walls extending generally vertically to the surface of the semiconductor substrate and such that surface portions of the semiconductor substrate are exposed at and adjacent said both opposing side walls of the temporary protection pattern; forming a first conductor layer, of a material that incorporates therein an impurity element of a first conductivity type, such that the conductor layer buries the temporary protection pattern therebeneath and is in intimate contact with said both opposing side walls of the temporary protection pattern and with the exposed surface portions of the semiconductor substrate at and adjacent both said opposing side walls of the temporary protection pattern; patterning the first conductor layer to form a pair of first type conductor regions adjacent to and in intimate contact with, respectively, said both opposing side walls of the temporary protection pattern, said step of patterning the first conductor layer comprising anisotropically etching the conductor layer selectively in a direction perpendicular to the major surface of said semiconductor substrate thereby to remove said conductor layer except for said pair of first type conductor regions, respectively located immediately adjacent to and in intimate contact with said opposing side walls of said temporary protection pattern; removing the temporary protection pattern selectively with respect to said pair of first type conductor regions and such that said pair of first type conductor regions remains on, and in intimate contact with, the semiconductor layer such that each of said pair of first type conductor regions has an exposed side wall that extends generally vertically to the surface of the semiconductor substrate; forming a second conductor layer such that the second conductor layer buries said pair of first type conductor regions therebeneath; patterning the second conductor layer such that a potion of the second conductor layer remains, between said pair of first type conductor regions, as a second type conductor region; and forming first diffusion regions in the semiconductor substrate, respectively in correspondence to major surface portions thereof on which said pair of first type conductor regions are provided, by causing diffusion thereinto of said impurity element.