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US5267204A
Expired / Lapsed
US
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Method and circuitry for masking data in a memory device
Assignee: Texas Instruments Inc
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Filing: 1991-10-18
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Granted: 1993-11-30
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Expires: 2011-10-18
Abstract
Abstract A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.
Inventors
- 👤 Benjamin H. Ashmore, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:44
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
136 words
Circuitry for masking data in a memory device, comprising: detection circuitry coupled to the memory device for detecting whether the data state of at least one failed bit location within the memory device is equal to the data state of a corresponding bit within input data; selection circuitry coupled to said detection circuitry and to the memory device for writing data to the memory device, said data selectively inverted from said input data based upon an output of said detection circuitry and for selectively setting an inversion bit within the memory device to indicate whether said written data is inverted from said input data; and test circuitry coupled to the memory device for reading the memory device to determine whether said written data and said selectively set inversion bit are properly stored in the memory device.
Claim 2
Dependent Claim
136 words
Circuitry for masking data in a memory device, comprising: detection circuitry coupled to the memory device for detecting whether the data state of at least one failed bit location within the memory device is equal to the data state of a corresponding bit within input data; selection circuitry coupled to said detection circuitry and to the memory device for writing data to the memory device, said data selectively inverted from said input data based upon an output of said detection circuitry and for selectively setting an inversion bit within the memory device to indicate whether said written data is inverted from said input data; and test circuitry coupled to the memory device for reading the memory device to determine whether said written data and said selectively set inversion bit are properly stored in the memory device.
Claim 3
Dependent Claim
39 words
The circuitry of claim 1 and further comprising signal circuitry coupled to said test circuitry for signalling an error condition if any said written data and said selectively set inversion bit are not properly stored in the memory device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-29 | 1997-05-31 | 1997-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-29 | 2005-05-31 | 2005-11-30 | $7700.00 | Window Closed / Lapsed |