Sense amplifier control circuit of a semiconductor memory device

Claim 2

A sense amplifier control circuit of a semiconductor memory device, said semiconductor memory device having a sense amplifier and a first sense amplifier driver, which are operated by a given control signal, comprising: a driver control circuit connected to transfer an output thereof to a control terminal of said first sense amplifier driver, for constantly maintaining a current flowing into said first sense amplifier driver; a bias circuit connected to transfer an output thereof to a control terminal of a driving element of said driver control circuit, for constantly maintaining a current flowing into said driving element, regardless of an increase and decrease of an external power voltage; and means connected to receive a voltage applied to said sense amplifier and to transfer an output thereof to said driver control circuit and said bias circuit, for driving said driver control circuit and bias circuit.

Claim 3

A sense amplifier control circuit as claimed in claim 1, wherein said first sense amplifier driver is comprised of a PMOS transistor.

Claim 4

A sense amplifier control circuit as claimed in claim 1, wherein said driver control circuit comprises: a first PMOS transistor having a source connected to a first power voltage and having a gate connected to a first input line; a first NMOS transistor connected, by a gate thereof, to said first input line; an output line commonly connected to a common terminal of said first PMOS and first NMOS transistors and connected to said control terminal of said first sense amplifier driver; a second NMOS transistor having a channel connected between said first NMOS transistor and a ground voltage, and having a gate connected to a second input line; and means connected between said first power voltage and said output line, for constantly maintaining a current flowing into said first and second NMOS transistors.

Claim 5

A sense amplifier control circuit as claimed in claim 3, wherein said current maintaining means comprises: a second PMOS transistor having a source connected to said first power voltage and having diode-connected gate and drain; and a third PMOS transistor having a channel connected between said drain of said second PMOS transistor and said output line, and having a gate connected to said ground voltage.

Claim 6

A sense amplifier control circuit as claimed in claim 3 or 4, wherein said first power voltage is of an external power voltage having a given first level.

Claim 7

A sense amplifier control circuit as claimed in claim 4, wherein said bias circuit comprises: a fourth PMOS transistor having a source connected to a second power voltage and having a gate connected to said ground voltage; a third NMOS transistor having a drain connected to a drain of said fourth PMOS transistor and a gate connected to said first input line; a first output node commonly connected to a common terminal of said fourth PMOS and third NMOS transistors; and a fourth NMOS transistor having a drain and gate diode-connected to said source of said third NMOS transistor and having a source connected to said ground voltage.

Claim 8

A sense amplifier control circuit as claimed in claim 6, wherein said second power voltage is of an internal power voltage having a given second level.

Claim 9

A sense amplifier control circuit as claimed in claim 6, wherein said driving means comprises: a third input line connected to a sense amplifier enable node, said sense amplifier enable node being connected to one terminal of a channel of said first sense amplifier driver; a fourth input line for applying a given reference voltage; a fifth input line for applying a given clock signal; a comparator having a second output node; and a trigger circuit having an input node connected to said second output node of said comparator and having a third output node commonly connected to said first input line of said bias circuit and said driver control circuit.

Claim 10

A sense amplifier control circuit as claimed in claim 8, wherein said reference voltage is a level of said second power voltage.

Claim 11

A sense amplifier control circuit as claimed in claim 8, wherein said clock signal is generated after a second sense amplifier driver is driven.

Claim 12

A sense amplifier control circuit as claimed in claim 10, wherein said second sense amplifier driver is a NMOS sense amplifier driver.

Claim 13

A sense amplifier control circuit as claimed in claim 8, wherein said comparator comprises: a fifth PMOS transistor having a source connected to said first power voltage and having diode-connected gate and drain; a sixth PMOS transistor having a source connected to said first power voltage and having a gate connected to said gate of said fifth PMOS transistor; a fifth NMOS transistor having a gate connected to said third input line and having a drain connected to said drain of said fifth PMOS transistor; a sixth NMOS transistor having a gate connected to said fourth input line and having a drain connected to a drain of said fifth PMOS transistor; said second output node connected to a common terminal of said sixth PMOS and sixth NMOS transistors; and a seventh NMOS transistor having a drain commonly connected to each source of said fifth and sixth NMOS transistors, a gate connected to said fifth input line and a source connected to said ground voltage.

Claim 14

A sense amplifier control circuit as claimed in claim 8, wherein said trigger circuit comprises: a seventh PMOS transistor having a source connect to said first power voltage and a gate connected to said input node; a eighth NMOS transistor having a source connected to said ground voltage and a gate connected to said input node; and said third output node commonly connected to each drain of said seventh PMOS and eighth NMOS transistors.

Claim 15

A sense amplifier control circuit capable of improving a device characteristic of a call, by adjusting a voltage of a first power source into a given level, and by applying the voltage of said given level to said cell, comprising: a comparator for comparing said voltage applied to said cell with a reference voltage and producing an output in dependence upon a clock signal; a level shift circuit for shifting a voltage potential of said clock signal; means controlled by an output of said level shift circuit, for enabling and disabling said output of said comparator; a trigger circuit for inverting said output of said comparator; a driver control circuit coupled to receive an output of said trigger circuit, for maintaining a current flowing into a first sense amplifier driver at said a given level, said driver control circuit having an output terminal being connected to a control terminal of said first sense amplifier driver; and a bias circuit for maintaining said current flowing into driving elements of said driver control circuit.

Claim 16

A sense amplifier control circuit capable of improving a device characteristic of a call, by adjusting a voltage of a first power source into a given level, and by applying the voltage of said given level to said cell, comprising: a comparator for comparing said voltage applied to said cell with a reference voltage and producing an output in dependence upon a clock signal; a level shift circuit for shifting a voltage potential of said clock signal; means controlled by an output of said level shift circuit, for enabling and disabling said output of said comparator; a trigger circuit for inverting said output of said comparator; a driver control circuit coupled to receive an output of said trigger circuit, for maintaining a current flowing into a first sense amplifier driver at said a given level, said driver control circuit having an output terminal being connected to a control terminal of said first sense amplifier driver; and a bias circuit for maintaining said current flowing into driving elements of said driver control circuit.

Claim 17

A sense amplifier control circuit as claimed in claim 14, wherein said first and second power voltage is 5 V and 4 V, respectively and said reference voltage is 4 V.

Claim 18

A sense amplifier control circuit as claimed in claim 14, wherein said clock signal is generated after a second sense amplifier driver is driven in response to a row address selected by a user.

Claim 19

A sense amplifier control circuit as claimed in claim 16, wherein said second sense amplifier driver is a NMOS sense amplifier driver.

Claim 20

A sense amplifier control circuit as claimed in claim 14, wherein said level shift circuit comprises: a first PMOS transistor having a source connected to said first power voltage; a second PMOS transistor having a source connected to said first power voltage; a first NMOS transistor having a gate connected to said clock signal, a source connected to ground voltage and a drain commonly connected to a drain of said first PMOS transistor and a gate of said second PMOS transistor; an inverter having an input terminal connected to said clock signal and a control input terminal connected to said second power voltage; a second NMOS transistor having a source connected to said ground voltage and a gate connected to an output terminal of said inverter; and an output node commonly connected to a gate of said first PMOS transistor and each drain of said second PMOS and said second NMOS transistors.

Claim 21

A sense amplifier control circuit as claimed in claim 14, wherein said enabling/disabling means is comprised of a PMOS transistor having a source connected to said first power voltage, a gate connected to said output node of said level shift circuit, and a drain connected to an output node of said comparator.

Claim 22

A sense amplifier control circuit for maintaining a voltage applied to a memory cell of a semiconductor memory device having a sense amplifier and a sense amplifier driver independently from variation of an external power voltage, said sense amplifier control circuit comprising: means for comparing the voltage applied to said memory cell with a reference voltage in dependence upon a sensing enable signal to provide a first resultant voltage; shifting means coupled to receive said sensing enable signal, for shifting voltage potential of said sensing enable signal from a first potential into a second potential to produce a shifted enable signal; means for enabling transmission of said first resultant voltage in dependence upon said shifted enable signal to provide a second resultant voltage; driver control means for driving current into said sense amplifier driver to maintain the voltage applied to said memory cell substantially at a defined voltage level irrespective of variation of said external power voltage; and biasing means responsive to said second resultant voltage signal, for generating a bias voltage for enabling said driver control means to maintain said voltage applied to said memory cell substantially at said defined voltage level.

Claim 23

A sense amplifier control circuit for maintaining a voltage applied to a memory cell of a semiconductor memory device having a sense amplifier and a sense amplifier driver independently from variation of an external power voltage, said sense amplifier control circuit comprising: means for comparing the voltage applied to said memory cell with a reference voltage in dependence upon a sensing enable signal to provide a first resultant voltage; shifting means coupled to receive said sensing enable signal, for shifting voltage potential of said sensing enable signal from a first potential into a second potential to produce a shifted enable signal; means for enabling transmission of said first resultant voltage in dependence upon said shifted enable signal to provide a second resultant voltage; driver control means for driving current into said sense amplifier driver to maintain the voltage applied to said memory cell substantially at a defined voltage level irrespective of variation of said external power voltage; and biasing means responsive to said second resultant voltage signal, for generating a bias voltage for enabling said driver control means to maintain said voltage applied to said memory cell substantially at said defined voltage level.

Claim 24

The sense amplifier control circuit as claimed in claim 20, wherein said comparing means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel and a control electrode respectively coupled to a first node; a second transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel coupled to an output terminal for providing said first resultant voltage, and a control electrode coupled to said first node; a third transistor having a first electrode of a principal electrically conducting channel coupled to said first node, a second electrode of said principal electrically conducting channel coupled to a second node and a control electrode coupled to receive the voltage applied to said memory cell; a fourth transistor having a first electrode of a principal electrically conducting channel coupled to said second node, a second electrode of said principal electrically conducting channel connected to ground and a control electrode coupled to receive said sensing enable signal; and a fifth transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to said second node and a control electrode coupled to receive said reference voltage.

Claim 25

The sense amplifier control circuit as claimed in claim 20, wherein said shifting means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage and a second electrode of said principal electrically conducting channel coupled to a first node; a second transistor having a first electrode of a principal electrically conducting channel coupled to said first node and a second electrode of said principal electrically conducting channel coupled to ground; a third transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage and a second electrode of said principal electrically conducting channel coupled to an output terminal for providing said shifted enable signal; a fourth transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal and a second electrode of said principal electrically conducting channel connected to ground; a control electrode of said first transistor being coupled to said output terminal; a control electrode of said third transistor being coupled to said first node; a control electrode of said second transistor being coupled to receive said sensing enable signal; and an inverter being coupled to an internal power voltage and interposed between control electrodes of said second and fourth transistors.

Claim 26

The sense amplifier control circuit as claimed in claim 20, wherein said biasing means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to an internal power voltage, a second electrode of said principal electrically conducting channel coupled to an output terminal for generating said bias voltage and a control electrode coupled to ground; a second transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to a first node and a control electrode coupled to receive said second resultant voltage; and a third transistor having a first electrode of a principal electrically conducting channel coupled to said first node, a second electrode of said principal electrically conducting channel coupled to ground and a control electrode coupled to said first node.

Claim 27

The sense amplifier control circuit as claimed in claim 20, wherein said driver control means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel coupled to an output terminal and a control electrode coupled to receive said second resultant voltage; a second transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to a first node and a control electrode coupled to receive said second resultant voltage; a third transistor having a first electrode of a principal electrically conducting channel coupled to said first node, a second electrode of said principal electrically conducting channel coupled to ground and a control electrode coupled to receive said bias voltage; a fourth transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel and a control electrode coupled to a second node; and a fifth transistor having a first electrode of a principal electrically conducting channel coupled to said second node, a second electrode of said principal electrically conducting channel coupled to said output terminal and a control electrode coupled to ground.

Claim 28

The sense amplifier control circuit as claimed in claim 20, wherein said enabling means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel coupled to receive said first resultant voltage and a control electrode coupled to receive said shifted enable signal; a second transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage and a second electrode of said principal electrically conducting channel coupled to an output terminal for providing said second resultant voltage; a third transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal and a second electrode of said principal electrically conducting channel coupled to ground; and control electrodes of said second and third transistors being coupled to receive said first resultant voltage.

Claim 29

The sense amplifier control circuit as claimed in claim 20, wherein said external power voltage is 5 volts, said reference voltage is 4 volts, and the first potential of said sensing enable signal is said reference voltage of 4 volts and the second potential of said sensing enable signal is said external power voltage of 5 volts.

Claim 30

The sense amplifier control circuit as claimed in claim 26, wherein said defined voltage level of the voltage applied to said memory cell is 4 volts.

Claim 31

A sense amplifier control circuit, comprising: an array of memory cells; a plurality of pairs of bit lines, each bit line pair of said pairs of bit lines being coupled to said memory cells; sense amplifier driver means for driving a voltage applied to said memory cells via said bit line pair; means for providing a sense amplifier enable signal representative of potential of the voltage applied to said memory cells from said bit line pair; means for determining the voltage applied to said memory cells by comparing a voltage potential of said sense amplifier enable signal with a reference voltage in dependence upon a sensing clock signal to provide a first resultant voltage; means for shifting voltage potential of said sensing clock signal from a first voltage potential into a second voltage potential to produce a shifted clock signal; means for enabling transmission of said first resultant voltage in dependence upon said shifted clock signal to provide a second resultant voltage; driver control means for driving current into said sense amplifier driver means to maintain the voltage applied to said memory cells substantially at a defined voltage level; and biasing means responsive to said second resultant voltage signal, for generating a bias voltage for enabling said driver control means to maintain said voltage applied to said memory cells substantially at said defined voltage level.

Claim 32

A sense amplifier control circuit, comprising: an array of memory cells; a plurality of pairs of bit lines, each bit line pair of said pairs of bit lines being coupled to said memory cells; sense amplifier driver means for driving a voltage applied to said memory cells via said bit line pair; means for providing a sense amplifier enable signal representative of potential of the voltage applied to said memory cells from said bit line pair; means for determining the voltage applied to said memory cells by comparing a voltage potential of said sense amplifier enable signal with a reference voltage in dependence upon a sensing clock signal to provide a first resultant voltage; means for shifting voltage potential of said sensing clock signal from a first voltage potential into a second voltage potential to produce a shifted clock signal; means for enabling transmission of said first resultant voltage in dependence upon said shifted clock signal to provide a second resultant voltage; driver control means for driving current into said sense amplifier driver means to maintain the voltage applied to said memory cells substantially at a defined voltage level; and biasing means responsive to said second resultant voltage signal, for generating a bias voltage for enabling said driver control means to maintain said voltage applied to said memory cells substantially at said defined voltage level.

Claim 33

The sense amplifier control circuit as claimed in claim 28, wherein said comparing means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to an external power supply, a second electrode of said principal electrically conducting channel and a control electrode respectively coupled to a first node; a second transistor having a first electrode of a principal electrically conducting channel coupled to an external power supply, a second electrode of said principal electrically conducting channel coupled to an output terminal and a control electrode coupled to said first node; a third transistor having a first electrode of a principal electrically conducting channel coupled to said first node, a second electrode of said principal electrically conducting coupled to a second node and a control electrode coupled to receive said sense amplifier enable signal; a fourth transistor having a first electrode of a principal electrically conducting channel coupled to said second node, a second electrode of said principal electrically conducting channel connected to ground and a control electrode coupled to receive said sensing clock signal; and a fifth transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to said second node and a control electrode coupled to receive said reference voltage, and said shifting means comprises: a sixth transistor having a first electrode of a principal electrically conducting channel coupled to said external power supply and a second electrode of said principal electrically conducting channel coupled to a third node; a seventh transistor having a first electrode of a principal electrically conducting channel coupled to said third node and a second electrode of said principal electrically conducting channel coupled to ground; a eighth transistor having a first electrode of a principal electrically conducting channel coupled to said external power supply and a second electrode of said principal electrically conducting channel coupled to an output terminal; a ninth transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal and a second electrode of said principal electrically conducting channel connected to ground; a control electrode of said sixth transistor being coupled to said output terminal; a control electrode of said eighth transistor being coupled to said first node; a control electrode of said seventh transistor being coupled to receive said sensing clock signal; and an inverter being coupled to an internal voltage supply and interposed between control electrodes of said seventh and ninth transistors.

Claim 34

The sense amplifier control circuit as claimed in claim 28, wherein said biasing means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to an internal power voltage, a second electrode of said principal electrically conducting channel coupled to an output terminal for generating said bias voltage and a control electrode coupled to ground; a second transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to a first node and a control electrode coupled to receive said second resultant voltage; and a third transistor having a first electrode of a principal electrically conducting channel and a control electrode coupled to said first node, and a second electrode of said principal electrically conducting channel connected to ground. conducting channel coupled to an output terminal for generating said bias voltage and a control electrode coupled to ground; a second transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to a first node and a control electrode coupled to receive said second resultant voltage; and a third transistor having a first electrode of a principal electrically conducting channel and a control electrode coupled to said first node, and a second electrode of said principal electrically conducting channel connected to ground.

Claim 35

The sense amplifier control circuit as claimed in claim 28, wherein said driver control means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to an external power voltage, a second electrode of said principal electrically conducting channel coupled to an output terminal for providing an output signal to maintain the voltage applied to said memory cells, and a control electrode coupled to receive said second resultant voltage; a second transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal, a second electrode of said principal electrically conducting channel coupled to a first node and a control electrode coupled to receive said second resultant voltage; a third transistor having a first electrode of a principal electrically conducting channel coupled to said first node, a second electrode of said principal electrically conducting channel coupled to ground and a control electrode coupled to receive said bias voltage; a fourth transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage, a second electrode of said principal electrically conducting channel and a control electrode coupled to a second node; and a fifth transistor having a first electrode of a principal electrically conducting channel coupled to said second node, a second electrode of said principal electrically conducting channel coupled to said output terminal and a control electrode coupled to ground.

Claim 36

The sense amplifier control circuit as claimed in claim 28, wherein said enabling means comprises: a first transistor having a first electrode of a principal electrically conducting channel coupled to an external power voltage, a second electrode of said principal electrically conducting channel coupled to receive said first resultant voltage and a control electrode coupled to receive said shifted clock signal; a second transistor having a first electrode of a principal electrically conducting channel coupled to said external power voltage and a second electrode of said principal electrically conducting channel coupled to an output terminal for providing said second resultant voltage; a third transistor having a first electrode of a principal electrically conducting channel coupled to said output terminal and a second electrode of said principal electrically conducting channel coupled to ground; and control electrodes of said second and third transistors being coupled to receive said first resultant voltage.