Simultaneous search-write content addressable memory

Claim 1

An improved content addressable memory of the type which includes, a) a clock input terminal for receiving successive clock pulses, b) search input terminals for sequentially receiving search addresses in synchronization with said clock pulses, c) a plurality of address registers which selectively store said search addresses and, d) compare circuits respectively coupled to each of said registers, that generate MATCH signals which indicate when a search address on said search input terminals is the same as an address in said address registers; wherein the improvement comprises: a first address circuit, coupled to said search input terminals, which transfers said search addresses from said search input terminals to said plurality of compare circuits; a second address circuit, coupled to said search input terminals, which operates in parallel with said first address circuit and sends said search addresses from said search input terminals to said plurality of address registers with a predetermined time delay; and, a control circuit, that is coupled to said clock input terminal, said plurality of address registers and said compare circuits, which during a single clock cycle a) conditionally provides write signals that write enable a delayed search address from said second address circuit to be written into a selectable one of said address registers, and b) receives said MATCH signals, as they are generated by said compare circuits, which compares said delayed search address in said selectable one of said address registers with another search address from said first address circuit, and stores a control signal representative of the MATCH signals.