Method and circuit arrangement for content controlled addressing of a memory

Claim 3

A method according to claim 1 further characterized by establishing a predetermined address range, and interrupting said step of momentary new address number is the highest new address number falling within next predetermined address range.

Claim 4

A method according to claim 1 further characterized by said step of interrupting the continued addressing of said memory being accomplished by changing said addend value to "0".

Claim 5

A method according to claim 1 further characterized by providing a search word, upon each addressing of said memory comparing the data word stored at the addressed storage location with said search word, and interrupting further addressing of said memory in the event the result of such comparision is that the compared data word equals said seach word.

Claim 6

A method according to claim 4 further characterized by said step of interrupting further addressing of said memory being accomplished by changing said addend value to "0".

Claim 7

A method according to claim 1 further characterized by said memory being one wherein the data word stored at an addressed storage location is read out of said memory upon the appearance of a "Read" clock pulse at a read control terminal, providing a plurality of "Read" pulses for reading said memory, and upon the rear edge of each of said "Read" pulses performing said steps of adding said addend value to obtain a new address number and addressing said memory with said new address number.

Claim 8

A circuit for content controlled addressing of a memory, said circuit comprising: a memory having a plurality of addressable storage locations, each of which storage locations is capable of storing a data word and has associated with it a unique address number with the set of address nubmers associated with said plurality of storage locations being one wherein the address numbers are a sequence of numbers wherein each number is larger than the preceding one by a unit value, a memory addressing register, an adder having output terminals connected to said memory addressing register for supplying its output to said register as an address number, said adder also having a set of first addend input terminals and a set of second addend input terminals, a start address register connected to said first addend input terminals of said adder for supplying a start address number to said adder, an addend input register connected to said second addend input terminals of said adder for supplying an addend to said adder, and means for first addressing said memory by supplying said start address from said start address register to said adder and then from said adder to said memory addressing register and for then sequentially addressing of said memory by after each addressing causing said adder to add said addend from said addend register to the last used address number to produce a new address number supplied to said memory addressing register.

Claim 9

A circuit for content controlled addressing of a memory, said circuit comprising: a memory having a plurality of addressable storage locations, each of which storage locations is capable of storing a data word and has associated with it a unique address number with the set of address nubmers associated with said plurality of storage locations being one wherein the address numbers are a sequence of numbers wherein each number is larger than the preceding one by a unit value, a memory addressing register, an adder having output terminals connected to said memory addressing register for supplying its output to said register as an address number, said adder also having a set of first addend input terminals and a set of second addend input terminals, a start address register connected to said first addend input terminals of said adder for supplying a start address number to said adder, an addend input register connected to said second addend input terminals of said adder for supplying an addend to said adder, and means for first addressing said memory by supplying said start address from said start address register to said adder and then from said adder to said memory addressing register and for then sequentially addressing of said memory by after each addressing causing said adder to add said addend from said addend register to the last used address number to produce a new address number supplied to said memory addressing register.

Claim 10

A circuit as described in claim 7 further characterized by a summation register connected to the output terminals of said adder for holding address numbers outputted by said adder, and means for switching said summation register to said first addend terminals of said adder in place of said start address register.

Claim 11

A circuit as described in claims 8 further characterized by said addend register being connected to said second set of addend terminals through a multiplexer, said multiplexer having two groups of input terminals, one of said groups of input terminals being connected to said addend register and the other of said groups of said groups of input terminals being connected to zero potential.

Claim 12

A circuit as described in claim 8 further characterized by said memory having a read control terminal, means for applyiing "Read" pulses to said read control terminal and said summation register being controlled by said "Read" pulses.