High speed data transceiver

Claim 2

Bias voltage regulator circuitry utilizable for providing a bias voltage signal to a driver stage of a high speed data transceiver, the bias voltage regulator circuitry comprising: (a) a serial string that includes a plurality of diode-connected transistors and a resistive element serially connected between a supply voltage and ground; (b) a resistive network connected in parallel with the serial string between the supply voltage and ground, the resistive element having a resistance which is an integer multiple of the resistance of the resistive network; and (c) a npn output transistor having its collector connected to the supply voltage, its base connected in common with the resistive network and ground, and its emitter connected to provide the bias voltage signal whereby the bias voltage signal is independent of the value of the supply voltage and changes inversely with temperature.

Claim 3

Bias voltage regulator circuitry as in claim 1 wherein the serial string has a voltage drop of 5 V BE and the resistance of the resistive element in the serial string is eight times the resistance of the resistive network whereby the bias voltage signal remains 4 V BE above ground.

Claim 4

Driver stage circuitry utilizable in a high speed data transceiver, the driver stage circuitry comprising: (a) an input node that receives a driver stage data input signal; (b) an output node that provides a driver stage output signal; (c) an n-channel output transistor that provides the driver stage output signal to the driver node; (d) switching means connected between the input node and the base of the n-channel output transistor such that when the input signal is logic high, the switching means provides base driver to the n-channel output transistor to turn on said output transistor, and when the input signal is logic low, the switching means holds the output transistor off; and (e) first capacitive means connected between the input node and the switching means for providing current to the base of the n-channel output transistor when the input signal transitions from logic low to logic high.

Claim 5

Driver stage circuitry utilizable in a high speed data transceiver, the driver stage circuitry comprising: (a) an input node that receives a driver stage data input signal; (b) an output node that provides a driver stage output signal; (c) an n-channel output transistor that provides the driver stage output signal to the driver node; (d) switching means connected between the input node and the base of the n-channel output transistor such that when the input signal is logic high, the switching means provides base driver to the n-channel output transistor to turn on said output transistor, and when the input signal is logic low, the switching means holds the output transistor off; and (e) first capacitive means connected between the input node and the switching means for providing current to the base of the n-channel output transistor when the input signal transitions from logic low to logic high.

Claim 6

Driver stage circuitry in claim 3 and further comprising second capacitive means connected between the switching means and the output node for controlling the slew rate of the driver stage output signal.

Claim 7

Driver stage circuitry as in claim 3 and further comprising: (a) discharge capacitive means connected to the base of the n-channel output transistor; and (b) an output switch connected between the discharge capacitive means and ground and responsive to a high-to-low transition of the data input signal for discharging the discharging the discharge capacitive means whereby the discharge path from the base of the output transistor to ground via the discharge capacitive means and the output switch provides fast turn-off for the output transistor.

Claim 8

Receiver circuitry utilizable in a high speed data transceiver, the receiver circuitry comprising: (a) an input node for receiving a receiver input signal; (b) input stage means connected to the input node for converting the receiver input signal to a corresponding ECL differential signal pair comprising a first ECL signal and a second ECL signal; (c) ECL-to-TTL converter means responsive to the ECL differential signal pair for providing a corresponding TTL logic level signal, the ECL-to-TTL converter means including (i) a first npn converter stage input transistor having its collector connected to a supply voltage, its emitter connected to an internal node, and its base connected to receive the first ECL signal; (ii) a second npn converter stage input transistor having its collector connected to the supply voltage and its base connected to receive the second ECL signal; (iii) capacitive means connected to the emitter of the first converter stage input transistor; (iv) discharge means connected between the capacitive means and ground and between the emitter of the second converter stage input transistor and ground whereby a high-to-low transition of the first ECL signal causes the internal node to go to a TTL low logic level and a low-to-high transition of the first ECL signal causes the internal node to go to a TTL high logic level.

Claim 9

Receiver circuitry utilizable in a high speed data transceiver, the receiver circuitry comprising: (a) an input node for receiving a receiver input signal; (b) input stage means connected to the input node for converting the receiver input signal to a corresponding ECL differential signal pair comprising a first ECL signal and a second ECL signal; (c) ECL-to-TTL converter means responsive to the ECL differential signal pair for providing a corresponding TTL logic level signal, the ECL-to-TTL converter means including (i) a first npn converter stage input transistor having its collector connected to a supply voltage, its emitter connected to an internal node, and its base connected to receive the first ECL signal; (ii) a second npn converter stage input transistor having its collector connected to the supply voltage and its base connected to receive the second ECL signal; (iii) capacitive means connected to the emitter of the first converter stage input transistor; (iv) discharge means connected between the capacitive means and ground and between the emitter of the second converter stage input transistor and ground whereby a high-to-low transition of the first ECL signal causes the internal node to go to a TTL low logic level and a low-to-high transition of the first ECL signal causes the internal node to go to a TTL high logic level.

Claim 10

Receiver circuitry as in claim 6 and further including a TTL output buffer that comprises: (a) a npn phase split transistor having its base connected to the internal node, its emitter coupled to ground and its collector coupled to an output node; (b) a n-channel pull-down transistor having its drain connected to the collector of the phase split transistor, its source connected to ground and its gate coupled to a disable node such that an active high disable signal applied to the disable node turns on the pull-down transistor thereby placing the output node in a high impedance state; and (c) a p-channel cut-off transistor having its source connected to the supply voltage, its drain coupled to the collector of the phase split transistor and its gate connected to the disable node such that the active high disable signal applied to the disable node turns off the cut-off transistor thereby causing the output buffer to consume zero power when the output node is in the high impedance state.

Claim 11

Receiver circuitry as in claim 7 wherein the TTL output buffer relies on backplane transceiver logic ground as ground for the receiver circuitry.