ECL/TTL-CMOS translator bus interface architecture

Claim 2

A translation architecture for a signal processor for translation from one signal environment to another, said architecture comprising: a first input line for receiving a first control signal from a first signal environment; a second input line for receiving a second control signal from a second signal environment; logic circuitry coupled between said first and second input lines and a plurality of translator circuits, said logic circuitry transmitting a third control signal in response to receiving said first or said second control signal; and each said translator circuit receiving a respective data signal from said first signal environment and said third control signal and transmitting an output signal in said second signal environment.

Claim 3

The translation architecture of claim 1 wherein said logic circuitry comprises a logic element receiving as input an ECL logic signal and one of the set of a TTL logic signal and a CMOS logic signal and having an output.

Claim 4

The translation architecture of claim 1 wherein each said translator circuit is a three-state device.

Claim 5

The translation architecture of claim 1 wherein said first control signals are ECL control signals.

Claim 6

The translation architecture of claim 1 wherein said second control signals are comprised of one of the set of TTL and CMOS control signals.

Claim 7

A transceiver architecture for use in a computer processor, said architecture comprising: a first input line for receiving a first control signal having first logic levels; a second input line for receiving a second control signal having second logic levels; first buffer circuitry coupled between said first input line and a first plurality of translator circuits, each of said first plurality of translator circuits coupled to receive said first control signals from said first input line and a first data signal composed of said second logic levels and transmitting a first output signal composed of said first logic levels; and second buffer circuitry coupled between said second input line and a second plurality of translator circuits, each of said second plurality of translator circuits coupled to receive said second control signals from said second input line and a second data signal composed of first logic levels and transmitting a second output signal composed of said second logic levels.

Claim 8

A transceiver architecture for use in a computer processor, said architecture comprising: a first input line for receiving a first control signal having first logic levels; a second input line for receiving a second control signal having second logic levels; first buffer circuitry coupled between said first input line and a first plurality of translator circuits, each of said first plurality of translator circuits coupled to receive said first control signals from said first input line and a first data signal composed of said second logic levels and transmitting a first output signal composed of said first logic levels; and second buffer circuitry coupled between said second input line and a second plurality of translator circuits, each of said second plurality of translator circuits coupled to receive said second control signals from said second input line and a second data signal composed of first logic levels and transmitting a second output signal composed of said second logic levels.

Claim 9

The transceiver architecture of claim 6 wherein said first buffer circuitry is one of the set of an inverting amplifier circuit and a non-inverting amplifier circuit.

Claim 10

The transceiver architecture of claim 6 wherein said second buffer circuitry is one of the set of an inverting amplifier circuit and a non-inverting amplifier circuit.

Claim 11

The transceiver architecture of claim 6 wherein each said first and second translator circuit is a three-state device.

Claim 12

The transceiver architecture of claim 6 wherein said first logic levels are ECL logic levels and said second logic levels are composed of one of the set of TTL and CMOS logic levels.

Claim 13

A translating architecture for use in a data processing system, said architecture acting to store and translate signals in one environment to signals in another environment and comprising: a first input line receiving a first control signal from a first signal environment; a second input line receiving a second control signal from a second signal environment; first buffer circuitry coupled between said first input line and a plurality of storage registers, each said storage register receiving said first control signal and one of a plurality of data signals from said first signal environment, each said storage register having an output; and second buffer circuitry coupled between said second input line and a plurality of translator circuits, each of said translator circuits coupled to receive said second control signal and a respective one of said storage register outputs and outputting a signal in said second signal environment.

Claim 14

A translating architecture for use in a data processing system, said architecture acting to store and translate signals in one environment to signals in another environment and comprising: a first input line receiving a first control signal from a first signal environment; a second input line receiving a second control signal from a second signal environment; first buffer circuitry coupled between said first input line and a plurality of storage registers, each said storage register receiving said first control signal and one of a plurality of data signals from said first signal environment, each said storage register having an output; and second buffer circuitry coupled between said second input line and a plurality of translator circuits, each of said translator circuits coupled to receive said second control signal and a respective one of said storage register outputs and outputting a signal in said second signal environment.

Claim 15

The translating architecture of claim 11 wherein said first signal environment is composed of ECL logic level signals and said second signal environment is composed of one of the set of TTL and CMOS logic signal levels.

Claim 16

The translating architecture of claim 11 wherein said first signal environment is composed of one of the set of TTL and CMOS logic signal levels and said second signal environment is composed of ECL logic signal levels.

Claim 17

The translating architecture of claim 11 wherein each of said translator circuits is a three-state device.