Method of making stacked W-cell capacitor

Claim 1

A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: forming a dielectric layer superjacent the surface of said silicon substrate; creating an aligned buried contact location at a storage node junction in each said active area, wherein said aligned buried contact location is defined by a patterned photomask which exposes a portion of said first dielectric layer, said exposed dielectric layer being etched away to expose said storage node junction; forming a first conductive layer superadjacent the patterned dielectric layer, said first conductive layer making contact to said storage node junction at said buried contact location; patterning said first conductive layer to form a portion of a storage node plate at each said storage node junction, said storage node plate portion remaining in contact to said storage node junction at said buried contact location; isotropically etching a remaining portion of said dielectric layer to thereby expose an underneath portion of said patterned first conductive layer, said underneath portion extending from said storage node junction to a gap between two adjacent word lines; forming a second conductive layer superjacent said patterned first conductive layer and said exposed underneath first conductive layer portion, said second conductive layer combining with said first conductive layer; patterning and dry etching said second conductive layer to form a complete storage node plate at said storage node junction, said storage node plate having a multi-fingered cross-section; forming a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent existing substrate surface; and forming a third conductive layer adjacent and coextensive said cell dielectric layer to form a top cell.