Integrated circuit memory with isolation of column line portions through P-sense amplification period

Claim 2

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and at least one column; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a column line connecting cells in a column, said column line divided into a first portion and a second portion; timing signal generator means for providing a P-sense timing signal defining a P-sense period and an isolation timing signal defining an isolation period which begins prior to the beginning of said P-sense period and extends into said P-sense period, said isolation timing signal being related to whether the row being addressed by said row decoder means is connected to a cell connected to said first column line portion or a cell connected to said second column line portion; P-sense amplifier means connected to said column line and responsive to said P-sense timing signal for amplifying the signal on said column line during said P-sense period; and isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion and said P-sense amplifier means during said isolation period while a row line associated with said second column line portion is being addressed.

Claim 3

An integrated circuit memory as in claim 1 further comprising input/output means for connecting said second column line portion to a circuit external of said memory array and wherein: said P-sense timing signal comprises a first P-sense timing signal defining a first P-sense period and a second P-sense timing signal defining a second P-sense period; said P-sense amplifier means comprises first P-sense amplifier means connected to said first column line portion and responsive to said first P-sense timing signal for amplifying the signal on said first column line portion during said first P-sense period and second P-sense amplifier means connected to said second column line portion and responsive to said P-sense timing signal for amplifying the signal on said second column line portion during said second P-sense period; and said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion and said second P-sense amplifier means during said first P-sense period while a row line associated with said second column line portion is being addressed.

Claim 4

An integrated circuit memory as in claim 1 wherein: said P-sense timing signal comprises a first P-sense timing signal defining a first P-sense period and a second P-sense timing signal defining a second P-sense period; said timing signal generator means further comprises means for providing a refresh timing signal defining a refresh period; and said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion and said P-sense amplifier means during said second P-sense period while a row line associated with said second column line portion is being addressed during said refresh period, and second isolating means responsive to said isolation timing signal for isolating said second column line portion from said first column line portion and said P-sense amplifier means during said first P-sense period while a row line associated with said first column line portion is being addressed during said refresh period.

Claim 5

An integrated circuit memory as in claim 3 and further comprising an N-sense amplifier connected to said column line between said first isolating means and said second isolating means and wherein said P-sense amplifier means comprises first P-sense amplifier means connected to said first column line portion and responsive to said first P-sense timing signal for amplifying the signal on said first column line portion during said first P-sense period, and second P-sense amplifier means connected to said second column line portion and responsive to said second P-sense timing signal for amplifying the signal on said second column line portion during said second P-sense period.

Claim 6

An integrated circuit memory as in claim 1 wherein said timing signal generator means further comprises means for producing a row access signal which changes during said P-sense period, and said isolation period continues at least until said row access signal changes during said P-sense period.

Claim 7

An integrated circuit memory as in claim 5 wherein said timing signal generator means further comprises means for producing a signal defining a precharge period, and said isolation period continues at least until said precharge period.

Claim 8

An integrated circuit memory as in claim 6 wherein said isolation period extends into said precharge period.

Claim 9

An integrated circuit memory as in claim 1 and further comprising an N-sense amplifier, and wherein: said timing signal generator means further comprises means for providing an N-sense timing signal defining a N-sense period; said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion, said N-sense amplifier, and said P-sense amplifier means during said P-sense period while a row line associated with said second column line portion is being addressed, and second isolating means responsive to said isolation timing signal for isolating said second column line portion from said first column line portion and said N-sense amplifier during said N-sense amplifier period while a row line associated with said first column line portion is being addressed; and said N-sense amplifier is connected to said column line between said first isolating means and said second isolating means.

Claim 10

An integrated circuit as in claim 8 wherein said P-sense amplifier means comprises a P-sense amplifier connected to said column line between said first isolating means and said second isolating means.

Claim 11

An integrated circuit memory as in claim 9 wherein there are a plurality of said column lines, each column line is divided into a first portion and a second portion, and each column line has associated with it one of said N-sense amplifiers, one of said first isolating means, one of said second isolating means, and one of said P-sense amplifiers.

Claim 12

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and at least one column; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a column line connecting cells in a column, said column line divided into a first portion and a second portion; input/output means for connecting said first column line portion to a circuit external of said memory array; timing signal generator means for providing a first P-sense timing signal defining a first P-sense period, a second P-sense timing signal defining a second P-sense period, and an isolation timing signal related to whether the row being addressed by said row decoder means is connected to a cell connected to said first column line portion or a cell connected to said second column line portion; first P-sense amplifier means responsive to said first P-sense timing signal for amplifying the signal on said first column line portion during said first P-sense period; second P-sense amplifier comprises means responsive to said P-sense timing signal for amplifying the signal on said second column line portion during said second P-sense period; isolating means responsive to said isolation timing signal for isolating said second column line portion from said first column line portion and said first P-sense amplifier during said first P-sense period while a row line associated with said first column line portion is being addressed.

Claim 13

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and at least one column; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a column line connecting cells in a column, said column line divided into a first portion and a second portion; input/output means for connecting said first column line portion to a circuit external of said memory array; timing signal generator means for providing a first P-sense timing signal defining a first P-sense period, a second P-sense timing signal defining a second P-sense period, and an isolation timing signal related to whether the row being addressed by said row decoder means is connected to a cell connected to said first column line portion or a cell connected to said second column line portion; first P-sense amplifier means responsive to said first P-sense timing signal for amplifying the signal on said first column line portion during said first P-sense period; second P-sense amplifier comprises means responsive to said P-sense timing signal for amplifying the signal on said second column line portion during said second P-sense period; isolating means responsive to said isolation timing signal for isolating said second column line portion from said first column line portion and said first P-sense amplifier during said first P-sense period while a row line associated with said first column line portion is being addressed.

Claim 14

An integrated circuit memory as in claim 11 and further comprising an N-sense amplifier connected to said column line between said first isolating means and said second isolating means, and wherein: said timing signal generator means further comprises means for providing a refresh timing signal defining a refresh period; said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion, said N-sense amplifier, and said second P-sense amplifier means during said second P-sense period while a row line associated with said second column line portion is being addressed during said refresh period; and second isolating means responsive to said isolation timing signal for isolating said second column line portion from said first column line portion, said N-sense amplifier, and said first P-sense amplifier means during said first P-sense period while a row line associated with said first column line portion is being addressed during said refresh period.

Claim 15

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and columns; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a first column line pair comprising a first column line connecting cells in one column and a second column line connecting cells in an adjacent column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves; timing signal generator means for providing a P-sense timing signal defining a P-sense period and an isolation timing signal related to whether the row being addressed by said row decoder means is connected to a cell connected to said first pair of column line halves or a cell connected to said second pair of column line halves; P-sense amplifier means oonnected between said column line pair and responsive to said P-sense timing signal for amplifying the signal on said column line pair during said P-sense period; and isolating means responsive to said isolation timing signal for isolating said first pair of column line halves from said second pair of column line halves and said P-sense amplifier means during said P-sense period while a row line associated with said second pair of column line halves is being addressed.

Claim 16

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and columns; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a first column line pair comprising a first column line connecting cells in one column and a second column line connecting cells in an adjacent column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves; timing signal generator means for providing a P-sense timing signal defining a P-sense period and an isolation timing signal related to whether the row being addressed by said row decoder means is connected to a cell connected to said first pair of column line halves or a cell connected to said second pair of column line halves; P-sense amplifier means oonnected between said column line pair and responsive to said P-sense timing signal for amplifying the signal on said column line pair during said P-sense period; and isolating means responsive to said isolation timing signal for isolating said first pair of column line halves from said second pair of column line halves and said P-sense amplifier means during said P-sense period while a row line associated with said second pair of column line halves is being addressed.

Claim 17

An integrated circuit memory as in claim 13 further comprising DRAM input/output means for connecting said second pair of column line halves to a circuit external of said memory array and wherein: said P-sense timing signal comprises a first P-sense timing signal defining a first P-sense period and a second P-sense timing signal defining a second P-sense period; said P-sense amplifier means comprises first P-sense amplifier means connected to said first pair of column line halves and responsive to said first P-sense timing signal for amplifying the signal on said first pair of column line halves during said first P-sense period and second P-sense amplifier means connected to said second pair of column line halves and responsive to said P-sense timing signal for amplifying the signal on said second pair of column line halves during said second P-sense period; said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first pair of column line halves from said second pair of column line halves and said second P-sense amplifier means during said first P-sense period while a row line associated with said second pair of column line halves is being addressed.

Claim 18

An integrated circuit memory as in claim 14 further comprising VRAM input/output means for connecting said first pair of column line halves to a circuit external of said memory array and wherein said isolating means further comprises second isolating means responsive to said isolation timing signal for isolating said second pair of column line halves from said first pair of column line halves and said first P-sense amplifier means during said first P-sense period while a row line associated with said first column line portion is being addressed.

Claim 19

An integrated circuit memory as in claim 15 wherein: said timing signal generator means further comprises means for providing a refresh timing signal defining a refresh period; said first isolating means comprises means responsive to said isolation timing signal for isolating said first pair of column line halves from said second pair of column line halves and said second P-sense amplifier means during said second P-sense period while a row line associated with said second pair of column line halves is being addressed during said refresh period; and said second isolating means comprises means responsive to said isolation timing signal for isolating said second pair of column line halves from said first pair column line halves and said first P-sense amplifier means during said first P-sense period while a row line associated with said first pair of column line halves is being addressed during said refresh period.

Claim 20

An integrated circuit memory as in claim 16 and further comprising an N-sense amplifier connected across said column line pair between said first isolating means and said second isolating means.

Claim 21

An integrated circuit memory as in claim 17 wherein there are a plurality of said column line pairs, each column line pair is divided into a first pair of column line halves and a second pair of column line halves, and each column line pair has associated with it one of said N-sense amplifiers, one of said first isolating means, one of said second isolating means, one of said first P-sense amplifier means, and one of said second P-sense amplifier means.

Claim 22

An integrated circuit memory as in claim 13 and further comprising an N-sense amplifier, and wherein: said timing signal generator means further comprises means for providing an N-sense timing signal defining a N-sense period; said isolating means comprises first isolating means responsive to said isolation timing signal for isolating said first pair of column line halves from said second pair of column line halves, said N-sense amplifier, and said P-sense amplifier means during said P-sense period while a row line associated with said second pair of column line halves is being addressed, and second isolating means responsive to said isolation timing signal for isolating said second pair of column line halves from said first pair of column line halves and said N-sense amplifier during said N-sense amplifier period while a row line associated with said first pair of column line halves is being addressed; said N-sense amplifier is connected to said column line pair between said first isolating means and said second isolating means; and said P-sense amplifier means comprises a P-sense amplifier connected to said column line pair between said first isolating means and said second isolating means.

Claim 23

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and at least one column; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a column line connecting cells in a column, said column line divided into a first portion and a second portion; an amplifier; timing signal generator means for providing a row access signal which changes near the beginning of an access cycle accessing one or more of said cells and then returns to its original value later in said access cycle, and amplifier signal defining an amplifying period, and an isolation timing signal defining an isolation period, said isolation timing signal being related to whether the row being addressed by said row decoder means is connected to a cell connected to said first column line portion or a cell connected to said second column line portion, and said isolation period beginning prior to said amplifying period and continuing at least until said row access signal returns to its original value; isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion and said amplifier during said isolation period while a row line associated with said second column line portion is being addressed.

Claim 24

An integrated circuit memory comprising: an array of memory cells arranged in a plurality of rows and at least one column; a plurality of row lines, each row line connecting cells in a row; row decoder means for addressing one of said rows in response to a row address signal; a column line connecting cells in a column, said column line divided into a first portion and a second portion; an amplifier; timing signal generator means for providing a row access signal which changes near the beginning of an access cycle accessing one or more of said cells and then returns to its original value later in said access cycle, and amplifier signal defining an amplifying period, and an isolation timing signal defining an isolation period, said isolation timing signal being related to whether the row being addressed by said row decoder means is connected to a cell connected to said first column line portion or a cell connected to said second column line portion, and said isolation period beginning prior to said amplifying period and continuing at least until said row access signal returns to its original value; isolating means responsive to said isolation timing signal for isolating said first column line portion from said second column line portion and said amplifier during said isolation period while a row line associated with said second column line portion is being addressed.

Claim 25

An integrated circuit memory as in claim 20 wherein said timing signal generator means further comprises means for producing a signal defining a precharge period, and said isolation period continues at least until said precharge period.

Claim 26

An integrated circuit memory as in claim 21 wherein said isolation period extends into said precharge period.