Computer system peripheral connection pulse filtering technique and circuit

Claim 2

In a computer system having a microcomputer unit with a port operating in accordance with a SCSI standard connected to one or more peripheral devices over a length of multi-conductor cable, one conductor of which is a request line from the peripherals to the microcomputer unit and another is an acknowledge line from the microcomputer unit to the peripherals, a pulse filtering circuit provided as part of the microcomputer unit and connected in at least the request line, comprising: means connected to the request line for preventing pulses of less than a first fixed duration thereon from reaching a first circuit node while allowing pulses of greater than said first fixed duration on the request line to reach said first circuit node, thereby to suppress unintended pulses less than said first fixed duration that might appear in the request line, means connected to said first circuit node for delaying by a second fixed duration propagation of the pulses greater than said first fixed duration from the first circuit node to a second node, means responsive to a trailing edge of pulses at the first circuit node for generating a pulse at a third circuit node having a third fixed duration, and means connected to said second and third circuit nodes for passing an initial segment of the delayed pulses at the second circuit node to the microcomputer while suppressing ending segments of said delayed pulses during the third fixed duration of the pulses at the third circuit node, thereby to shield the microcomputer from undesirable effects that can occur at trailing edges of the delayed pulses as a result of reflections of pulses on the request line.

Claim 3

The combination according to claim 1 wherein said pulse preventing means includes an OR-gate having as inputs said request line and an output of a first delay circuit that in turn has an input connected with said request line, whereby signals at said request line occur at the output of said first delay circuit with said first fixed duration in delay, an output of said OR-gate being connected to said first circuit node.

Claim 4

The combination according to claim 1 wherein said pulse generating means includes a one-shot multivibrator that is triggerable at an input by trailing edges of pulses at the first circuit node.

Claim 5

The combination according to claim 3 which additionally comprises an OR-gate having an output connected to the one-shot multivibrator input and two inputs, one of said OR-gate inputs being connected to the first circuit node and another of said OR-gate inputs being connected to said third circuit node.

Claim 6

The combination according to claim 1 wherein said pulse segment passing means includes an OR-gate having separate inputs connected to said second and third circuit nodes and an output providing signals to said microcomputer.

Claim 7

The combination according to claim 1 wherein said third fixed duration is less than said second fixed duration.

Claim 8

A single integrated circuit chip adapted for use in a computer system, comprising: a first set of terminals adapted for connection with a data bus of the computer system, a serial communication controller circuit connected between said first set of terminals and a second set of terminals adapted for connection with a communication device, a small computer system interface circuit connected between said first set of terminals and a third set of terminals adapted for connection with a peripheral device, said interface circuit adapted to respond to trailing edges of pulses received from a peripheral device on at least one of said third set of terminals, and a pulse filtering circuit connected between at least one terminal of said third set of terminals and said interface circuit, said pulse filtering circuit including means receiving a signal pulse from said at least one terminal for delaying said pulse by a set time, and additional means also receiving said signal pulse and responsive to a trailing edge thereof for cleanly terminating the delayed signal pulse substantially thereat, whereby any reflection or other noise in the signal pulse at about trailing edge is suppressed before being applied to said interface circuit.

Claim 9

A single integrated circuit chip adapted for use in a computer system, comprising: a first set of terminals adapted for connection with a data bus of the computer system, a serial communication controller circuit connected between said first set of terminals and a second set of terminals adapted for connection with a communication device, a small computer system interface circuit connected between said first set of terminals and a third set of terminals adapted for connection with a peripheral device, said interface circuit adapted to respond to trailing edges of pulses received from a peripheral device on at least one of said third set of terminals, and a pulse filtering circuit connected between at least one terminal of said third set of terminals and said interface circuit, said pulse filtering circuit including means receiving a signal pulse from said at least one terminal for delaying said pulse by a set time, and additional means also receiving said signal pulse and responsive to a trailing edge thereof for cleanly terminating the delayed signal pulse substantially thereat, whereby any reflection or other noise in the signal pulse at about trailing edge is suppressed before being applied to said interface circuit.

Claim 10

The circuit chip according to claim 7 wherein said pulse filtering circuit additionally includes means responsive to pulses received at said at least one terminal for preventing pulses of a duration less than said signal pulse from reaching said filtering means, thereby to suppress unintended received pulses.

Claim 11

A single integrated circuit chip adapted for use in a computer system, comprising: a first set of terminals adapted for connection with a data bus of the computer system, a serial communication controller circuit connected between said first set of terminals and a second set of terminals adapted for connection with a communication device, a small computer system interface circuit connected between said first set of terminals and a third set of terminals adapted for connection with a peripheral device, said interface circuit adapted to respond to trailing edges of pulses received from a peripheral device on at least one terminal of said third set of terminals, and a pulse filtering circuit connected between said at least one terminal and said interface circuit, said pulse filtering circuit including: means connected to said at least one terminal for preventing pulses of less than a first fixed duration thereon from reaching a first circuit node while allowing pulses of greater than said first fixed duration at said at least one terminal to reach said first circuit node, thereby to suppress unintended pulses less than said first fixed duration that might appear at said at least one terminal, means connected to said second circuit node for delaying by a second fixed duration propagation of the pulses greater than said first fixed duration from the second circuit node to a third node, means responsive to a trailing edge of pulses at the first circuit node for generating pulses at a third circuit node having a third fixed duration, and means connected to said second and third circuit nodes for passing an initial segment of the delayed pulses at the second circuit node to said interface circuit while suppressing ending segments of said delayed pulses during the third fixed duration of the pulses at the third circuit node, thereby to suppress undesirable effects as might exist about trailing edges of the delayed pulses.

Claim 12

A single integrated circuit chip adapted for use in a computer system, comprising: a first set of terminals adapted for connection with a data bus of the computer system, a serial communication controller circuit connected between said first set of terminals and a second set of terminals adapted for connection with a communication device, a small computer system interface circuit connected between said first set of terminals and a third set of terminals adapted for connection with a peripheral device, said interface circuit adapted to respond to trailing edges of pulses received from a peripheral device on at least one terminal of said third set of terminals, and a pulse filtering circuit connected between said at least one terminal and said interface circuit, said pulse filtering circuit including: means connected to said at least one terminal for preventing pulses of less than a first fixed duration thereon from reaching a first circuit node while allowing pulses of greater than said first fixed duration at said at least one terminal to reach said first circuit node, thereby to suppress unintended pulses less than said first fixed duration that might appear at said at least one terminal, means connected to said second circuit node for delaying by a second fixed duration propagation of the pulses greater than said first fixed duration from the second circuit node to a third node, means responsive to a trailing edge of pulses at the first circuit node for generating pulses at a third circuit node having a third fixed duration, and means connected to said second and third circuit nodes for passing an initial segment of the delayed pulses at the second circuit node to said interface circuit while suppressing ending segments of said delayed pulses during the third fixed duration of the pulses at the third circuit node, thereby to suppress undesirable effects as might exist about trailing edges of the delayed pulses.

Claim 13

The circuit chip according to claim 9 wherein said third fixed duration is less than said second fixed duration.

Claim 14

The circuit chip according to claim 9 wherein said pulse preventing means includes an OR-gate having as inputs said at least one terminal and an output of a first delay circuit having an input connected with said at least one terminal, whereby signals at said at least one terminal occur at the output of said first delay circuit with said first fixed duration in delay, an output of said OR-gate being connected to said first circuit node.

Claim 15

The circuit chip according to claim 9 wherein said pulse generating means includes a one-shot multivibrator that is triggerable at an input by trailing edges of pulses at the first circuit node.

Claim 16

The circuit chip according to claim 12 which additionally comprises an OR-gate having an output connected to the one-shot multivibrator input and two inputs, one of said OR-gate inputs being connected to the first circuit node and another of said OR-gate inputs being connected to said third circuit node.

Claim 17

The circuit chip according to claim 9 wherein said pulse segment passing means includes an OR-gate having separate inputs connected to said second and third circuit nodes and an output providing signals to said interface circuit.