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US5263054A
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Method and system for interpolating baud rate timing recovery for asynchronous start stop protocol
Assignee: International Business Machines Corp
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Filing: 1992-05-21
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Granted: 1993-11-16
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Expires: 2012-05-21
Abstract
Abstract An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.
Inventors
- 👤 Gordon T. Davis
- 👤 Baiju D. Mandalia
- 👤 John C. Sinibaldi
- 👤 William M. Zevin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:51
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
134 words
A method for efficient computation of a demodulation process on a digital signal processor for a sampled signal, wherein the sampled signal includes a plurality of samples representing a plurality of bits, wherein each of the plurality of bits has a bit period, the method comprising: detecting a sampled signal; searching the sampled signal for an occurrence of a threshold crossing associated with a start bit; responsive to a detection of an occurrence of a threshold crossing, performing a linear interpolation to find a crossing point where the threshold crossing occurs; responsive to determining the crossing point where the threshold crossing occurs, determining a center of a start bit; and locating centers of subsequent bits using the center of the start bit and a bit period associated with each of the plurality of bits.
Claim 2
Independent Claim
134 words
A method for efficient computation of a demodulation process on a digital signal processor for a sampled signal, wherein the sampled signal includes a plurality of samples representing a plurality of bits, wherein each of the plurality of bits has a bit period, the method comprising: detecting a sampled signal; searching the sampled signal for an occurrence of a threshold crossing associated with a start bit; responsive to a detection of an occurrence of a threshold crossing, performing a linear interpolation to find a crossing point where the threshold crossing occurs; responsive to determining the crossing point where the threshold crossing occurs, determining a center of a start bit; and locating centers of subsequent bits using the center of the start bit and a bit period associated with each of the plurality of bits.
Claim 3
Dependent Claim
28 words
The method of claim 1, further comprising applying the sampled signal to an interpolating filter to add interpolation samples to the sampled signal before searching the sampled signal.
Claim 4
Dependent Claim
52 words
The method of claim 2, wherein the step of searching for an occurrence of a threshold crossing includes detecting a first sample before the occurrence of a threshold crossing and a second sample after the occurrence of a threshold crossing, wherein the first and second samples are separated by a demodulator delay.
Claim 5
Dependent Claim
39 words
The method of claim 3, wherein said of performing a linear interpolation to find a crossing point where the threshold crossing occurs includes utilizing the first and second samples to find the crossing point where the threshold crossing occurs.
Claim 6
Dependent Claim
19 words
The method of claim 2 further comprising testing samples representing a bit to determine whether the bit is valid.
Claim 7
Dependent Claim
36 words
The method of claim 1, wherein the step of determining a center of a start bit includes using the crossing point and one half of the bit period to determine the center of the start bit.
Claim 8
Independent Claim
150 words
An apparatus for efficient computation for efficient computation of a demodulation process on a digital signal processor for a sampled signal, wherein the sampled signal includes a plurality of samples representing has a plurality of bits, wherein each of the plurality of bits has a bit period, the apparatus comprising: detection means for detecting a sampled signal; means for searching the sampled signal for an occurrence of a threshold crossing associated with a start bit; means, responsive to a detection of an occurrence of a threshold crossing, for performing a linear interpolation to find a crossing point where the threshold crossing occurs; means, responsive to determining the crossing point where the threshold crossing occurs, for determining a center of a start bit; and location means for locating centers of subsequent bits using the center of the start bit and a bit period associated with each of the plurality of bits.
Claim 9
Independent Claim
150 words
An apparatus for efficient computation for efficient computation of a demodulation process on a digital signal processor for a sampled signal, wherein the sampled signal includes a plurality of samples representing has a plurality of bits, wherein each of the plurality of bits has a bit period, the apparatus comprising: detection means for detecting a sampled signal; means for searching the sampled signal for an occurrence of a threshold crossing associated with a start bit; means, responsive to a detection of an occurrence of a threshold crossing, for performing a linear interpolation to find a crossing point where the threshold crossing occurs; means, responsive to determining the crossing point where the threshold crossing occurs, for determining a center of a start bit; and location means for locating centers of subsequent bits using the center of the start bit and a bit period associated with each of the plurality of bits.
Claim 10
Dependent Claim
30 words
The apparatus of claim 7, further comprising means for applying the sampled signal to an interpolating filter to add interpolation samples to the sampled signal before searching the sampled signal.
Claim 11
Dependent Claim
55 words
The apparatus of claim 8, wherein the means for searching for an occurrence of a threshold crossing includes detection means for detecting a first sample before the occurrence of a threshold crossing and a second sample after the occurrence of a threshold crossing, wherein the first and second samples are separated by a demodulator delay.
Claim 12
Dependent Claim
42 words
The apparatus of claim 9, wherein said means for performing a linear interpolation to find a crossing point where the threshold crossing occurs includes means for utilizing the first and second samples to find the crossing point where the threshold crossing occurs.
Claim 13
Dependent Claim
22 words
The apparatus of claim 10 further comprising testing means for testing samples representing a bit to determine whether the bit is valid.
Claim 14
Dependent Claim
36 words
The apparatus of claim 7, wherein the means for determining a center of a start bit includes using the crossing point and one half of the bit period to determine the center of the start bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |