Digital demodulation of frequency-shift keyed data signals

Claim 2

In a communications system encoding the states of a digital data signal in the discrete frequencies assumed by a transmitted carrier signal, a demodulator for recovering said data signal states from said carrier signal comprising means for measuring the duration of each cycle of said carrier signal, means for resolving eaCh duration measurement into a corresponding data-signal state, means jointly responsive to a change in resolved data-signal states and to the two most recent duration measurements for estimating the delay interval between the intermediate carriersignal transition and the true data-state transition, and variable means controlled by said estimating means for producing an output data transition delayed from the most recent carriersignal transition by said estimated delay interval.

Claim 3

The demodulator of claim 1 in which said duration measuring means performs duration measurements between alternate zero crossings of one sense only of said carrier signal and comprises a timing source providing clock pulses at a repetition frequency substantially higher than the highest frequency assumed by said carrier signal, a transition detector responsive to said carrier signal for providing pulses coincident with alternate zero crossings thereof, means resettable by pulses from said transition detector for counting said clock pulses, and means responsive to pulses from said transition detector for storing the counts corresponding to the two most recent duration measurements.

Claim 4

The demodulator of claim 1 in which said duration measuring means performs separate measurements between all positive-going and between all negative-going zero crossings of said carrier signal and comprises a timing source providing clock pulses at a repetition frequency substantially higher than the highest frequency assumed by said carrier signal, a transition detector responsive to said carrier signal for providing first and second pulse trains corresponding to respective positive-going and negative-going zero crossings of said carrier signal, first counting means resettable by pulses from said first pulse train for counting said clock pulses, second counting means resettable by pulses from said second pulse train for counting said clock pulses, first sampling means responsive to pulses of said first pulse train for sampling and storing counts corresponding to the two most recent duration measurements between consecutive positive-going zero-crossing transitions, second sampling means responsive to pulses of said second pulse train for sampling and storing counts corresponding to the two most recent duration measurements between consecutive negative-going zero-crossing transitions, first means for averaging corresponding counts for the most recent overlapping measurements derived from said first and second sampling means, and second means for averaging corresponding counts for the next prior overlapping measurements derived from said first and second sampling means.

Claim 5

The demodulator of claim 1 in which said estimating means comprises a transition detector responsive only to the zero crossing of said carrier signal coincident with a change in said resolved data signal states, first subtracting means for taking the difference between the duration measurement obtained before a threshold duration is reached and such threshold measurement, second subtracting means for taking the difference between consecutive duration measurements straddling the threshold duration, division means for obtaining the quotient between the outputs of said first and second subtracting means, and multiplying means for generating the delay interval between said coincident carrier signal transition and said true data-state transition as the product of said quotient and a duration corresponding to said threshold measurement.

Claim 6

The demodulator of claim 1 in which said variable delay unit comprises sample and hold means for storing the count corresponding to said delay interval, counting means whose count is initiated by said intermediate carrier-signal transition, and comparator means responsive to the coincidence of the count output of said counting means with the count from said sample and hold means for generating said oUtput data transition.

Claim 7

In a receiver for a frequency-shift keyed data transmission system in which sequential samples of the waves in a plurality of channels are time-division multiplexed into a serial bit stream, a demodulator comprising means for comparing the binary significance of bits corresponding to consecutive samples of each of the waves encoded in said bit stream to detect the occurrence of transitions defining the zero crossings of each frequency cycle for each channel, means for sequentially counting between transitions consecutively detected in the several channels as a measure of the duration of consecutive frequency cycles for each channel, means responsive to said transitions for storing duration counts derived by said counting means from each of said channels, means for resolving the counts between said transitions in each channel into a sequence of corresponding data states, means responsive to a change in consecutive data states in each channel for interpolating between the stored and present duration count for each channel to determine delay values between channel wave transitions and true data state transitions, and means for sequentially applying the delay values determined for the several channels to the most recent transition of each channel wave to generate output data transitions.

Claim 8

In a receiver for a frequency-shift keyed data transmission system in which sequential samples of the waves in a plurality of channels are time-division multiplexed into a serial bit stream, a demodulator comprising means for comparing the binary significance of bits corresponding to consecutive samples of each of the waves encoded in said bit stream to detect the occurrence of transitions defining the zero crossings of each frequency cycle for each channel, means for sequentially counting between transitions consecutively detected in the several channels as a measure of the duration of consecutive frequency cycles for each channel, means responsive to said transitions for storing duration counts derived by said counting means from each of said channels, means for resolving the counts between said transitions in each channel into a sequence of corresponding data states, means responsive to a change in consecutive data states in each channel for interpolating between the stored and present duration count for each channel to determine delay values between channel wave transitions and true data state transitions, and means for sequentially applying the delay values determined for the several channels to the most recent transition of each channel wave to generate output data transitions.

Claim 11

The method of claim 7 in which the duration of a received-signal cycle is taken as the average of overlapping measurements between consecutive pairs of alternately positive-going and negative-going zero crossings of said received signal.

Claim 12

The method of claim 7 in which the duration of a received-signal cycle is measured between consecutive zero crossings of the same polarity-seeking direction.

Claim 13

In an apparatus resolving the cycles of a frequency variant received signal into the discrete values of a digital signal by measuring the duration of said cycles, the method of reducing the phase jitter in said digital signal comprising the steps of: when one of said cycles is resolved to a different one of said values than the immediately preceding cycle, estimating the delay interval between the start of said cycle and the true transition in value of said digital signal, and delaying said digital signal by an amount equal to the estimated delay interval.

Claim 14

In an apparatus resolving the cycles of a frequency variant received signal into the discrete values of a digital signal by measuring the duration of said cycles, the method of reducing the phase jitter in said digital signal comprising the steps of: when one of said cycles is resolved to a different one of said values than the immediately preceding cycle, estimating the delay interval between the start of said cycle and the true transition in value of said digital signal, and delaying said digital signal by an amount equal to the estimated delay interval.

Claim 15

In an apparatus for resolving the cycles of a frequency variant received signal into the discrete values of a digital signal, said apparatus including means for measuring the duration of said cycles, an improvement for reducing phase jitter in said digital signal comprising: means responsive to a change in said digital signal for estimating the delay interval between the start of the most recently completed one of said cycles and the time during said cycle that the time transition in said digital signal should occur, and variable means controlled by said estimating means for delaying said digital signal by an amount equal to said delay interval.

Claim 16

In an apparatus for resolving the cycles of a frequency variant received signal into the discrete values of a digital signal, said apparatus including means for measuring the duration of said cycles, an improvement for reducing phase jitter in said digital signal comprising: means responsive to a change in said digital signal for estimating the delay interval between the start of the most recently completed one of said cycles and the time during said cycle that the time transition in said digital signal should occur, and variable means controlled by said estimating means for delaying said digital signal by an amount equal to said delay interval.