Extendable FIFO

Claim 2

An extendible FIFO comprising: a quasi-simultaneous clock detector for detecting the activation of read and write signals and generating first and second delayed signals in response thereto and a mask signal when said read and write signals are substantially simultaneously activated; a plurality of pointer circuits for receiving said first and second delayed signals and said mask signal and for generating particular clocks and load signals for performing a read operation in response to said first delayed signal, a write operation in response to said second delayed signal, or simultaneous read and write operations in response to said mask signal, depending on which of said first and second delayed signals and said mask signal are received by said pointer circuits; and a matrix of flip-flops organized into columns which are sequentially connected for receiving said clocks and load signals for controlling into which column data is to be written and for controlling the sequential transfer of data between columns.

Claim 3

An extendible FIFO comprising: a quasi-simultaneous clock detector for detecting the activation of read and write signals and generating first and second delayed signals in response thereto and a mask signal when said read and write signals are substantially simultaneously activated; a plurality of pointer circuits for receiving said first and second delayed signals and said mask signal and for generating a plurality of clocks and load signals in response thereto; and a matrix of flip-flops organized into columns which are sequentially connected for receiving said clocks and load signals for controlling into which column data is to be written and for controlling the sequential transfer of data between columns, said FIFO further comprising: a data-in line connected to said flip-flop matrix; and a plurality of multiplexers responsive to said load signals, each of said multiplexers having an output connected to one flip-flop column, a first input connected to a neighboring flip-flop column and a second input connected to said data-in line so that when said write signal is activated said pointer circuit associated with an empty flip-flop column closest to one end of the matrix generates a clock and load signal to write data from the data-in line therein and when said read signal is activated all of the pointer circuits generate a clock and load signal to transfer data from each corresponding flip-flop column into the adjacent column nearer to said one end, the flip-flop column closes to the one end outputting the data stored therein, so that data shifts one column towards said one end of said flip-flop matrix.

Claim 4

An extendible FIFO comprising: a quasi-simultaneous clock detector for detecting the activation of read and write signals and generating first and second delayed signals in response thereto and a mask signal when said read and write signals are substantially simultaneously activated; a plurality of pointer circuits for receiving said first and second delayed signals and said mask signal and for generating a plurality of clocks and load signals in response thereto; and a matrix of flip-flops organized into columns which are sequentially connected for receiving said clocks and load signals for controlling into which column data is to be written and for controlling the sequential transfer of data between columns, said FIFO further comprising: a data-in line connected to said flip-flop matrix; and a plurality of multiplexers responsive to said load signals, each of said multiplexers having an output connected to one flip-flop column, a first input connected to a neighboring flip-flop column and a second input connected to said data-in line so that when said write signal is activated said pointer circuit associated with an empty flip-flop column closest to one end of the matrix generates a clock and load signal to write data from the data-in line therein and when said read signal is activated all of the pointer circuits generate a clock and load signal to transfer data from each corresponding flip-flop column into the adjacent column nearer to said one end, the flip-flop column closes to the one end outputting the data stored therein, so that data shifts one column towards said one end of said flip-flop matrix.

Claim 5

The FIFO of claim 2 wherein the pointer circuits, in response to the activation of said mask signal, generate clock and load signals to substantially simultaneously shift by one column data stored in said columns towards said one end of said flip-flop matrix, the data stored in the column closest to said one end being output, and transferring data on said data-in line into the flip-flop column which stored the last data written to the FIFO prior to the activation of the mask signal.

Claim 6

An extendible FIFO comprising: a quasi-simultaneous clock detector for detecting the activation of read and write signals and generating first and second delayed signals in response thereto and a mask signal when said read and write signals are substantially simultaneously activated; a plurality of pointer circuits for receiving said first and second delayed signals and said mask signal and for generating a plurality of clocks and load signals in response thereto; and a matrix of flip-flops organized into columns which are sequentially connected for receiving said clocks and load signals for controlling into which column data is to be written and for controlling the sequential transfer of data between columns, wherein said quasi-simultaneous clock detector comprises: a high-level detector connected to said pointer circuits for receiving said read and write signals and for generating said mask signal when said read and write signals are activated substantially simultaneously; a first delay circuit for generating said first delayed signal in response to the write signal; and a second delay circuit for generating said second delayed signal in response to the read signal.

Claim 7

An extendible FIFO comprising: a quasi-simultaneous clock detector for detecting the activation of read and write signals and generating first and second delayed signals in response thereto and a mask signal when said read and write signals are substantially simultaneously activated; a plurality of pointer circuits for receiving said first and second delayed signals and said mask signal and for generating a plurality of clocks and load signals in response thereto; and a matrix of flip-flops organized into columns which are sequentially connected for receiving said clocks and load signals for controlling into which column data is to be written and for controlling the sequential transfer of data between columns, wherein said quasi-simultaneous clock detector comprises: a high-level detector connected to said pointer circuits for receiving said read and write signals and for generating said mask signal when said read and write signals are activated substantially simultaneously; a first delay circuit for generating said first delayed signal in response to the write signal; and a second delay circuit for generating said second delayed signal in response to the read signal.

Claim 8

The FIFO of claim 4 wherein the width of said mask signal pulse, the widths of said first and second delayed signal pulses and a delay period generated by said first and second delay circuits satisfy: Tp<Td Tm>Td+Tp where Td is the delay period generated by the first and second delay circuits, Tp is the width of the first and second delay signal pulses and Tm is the width of the mask signal pulse.