US5262341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Blanking aperture array and charged particle beam exposure method
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1992-12-16
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Granted: 1993-11-16
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Expires: 2012-12-16
Abstract
Abstract A blanking aperture array for use in a charged particle beam exposure has a substrate, at least m rows by n columns of apertures arranged two-dimensionally in the substrate, where each of the apertures have a pair of blanking electrodes and m and n are integers greater than one, and n m-bit shift registers provided on the substrate for applying voltages dependent on pattern data to m pairs of the blanking electrodes of the apertures in the ith column, where i=1, 2, . . . , n. The pattern data is related to a pattern which is to be exposed using the blanking aperture array.
Inventors
- 👤 Shunsuke Fueki
- 👤 Hiroshi Yasuda
- 👤 Kiichi Sakamoto
- 👤 Yasushi Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:37
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/02; H01J37/04; H01J37/045; H01J37/30; H01J37/302; H01J37/3023; H01J37/3026
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A method of producing a blanking aperture array comprising the steps of: preparing a stacked structure including a semiconductor substrate, an impurity diffusion layer formed on a top surface of said semiconductor substrate and an epitaxial layer formed on said impurity diffusion layer; forming a plurality of shift registers generally along a first direction and clock signal lines generally along a second direction on said epitaxial layer, each of said shift registers comprising a plurality of shift register parts which are coupled in series, each shift register part including an inverter and a gate, said clock signal lines being coupled to the gates of said shift register part, said first and second directions being mutually perpendicular; forming rows and columns of apertures between said shift registers and said clock signal lines, each of said apertures having a pair of blanking electrodes, said rows extending in said first direction, said columns extending in said second direction; and connecting one of the pair of blanking electrodes of each aperture to an output of a corresponding one of said shift register parts and the other of the pair of blanking electrodes of each aperture to a potential line
Claim 2
Independent Claim
195 words
A method of producing a blanking aperture array comprising the steps of: preparing a stacked structure including a semiconductor substrate, an impurity diffusion layer formed on a top surface of said semiconductor substrate and an epitaxial layer formed on said impurity diffusion layer; forming a plurality of shift registers generally along a first direction and clock signal lines generally along a second direction on said epitaxial layer, each of said shift registers comprising a plurality of shift register parts which are coupled in series, each shift register part including an inverter and a gate, said clock signal lines being coupled to the gates of said shift register part, said first and second directions being mutually perpendicular; forming rows and columns of apertures between said shift registers and said clock signal lines, each of said apertures having a pair of blanking electrodes, said rows extending in said first direction, said columns extending in said second direction; and connecting one of the pair of blanking electrodes of each aperture to an output of a corresponding one of said shift register parts and the other of the pair of blanking electrodes of each aperture to a potential line
Claim 3
Dependent Claim
116 words
The method of producing the blanking aperture array as claimed in claim 1 wherein said step of forming apertures includes the substeps of: forming a pair of grooves in said epitaxial layer which reach said semiconductor substrate at positions on both confronting sides of each aperture by a trench etching; forming an insulator layer on a surface of each pair of said grooves; filling an electrode material within each pair of said grooves; removing said epitaxial layer and said impurity diffusion layer between each of said pair of grooves by an etching; and forming an aperture by between each pair of said grooves by a taper etching made from a bottom surface of said semiconductor substrate.
Claim 4
Dependent Claim
57 words
The method of producing the blanking aperture array as claimed in claim 1 wherein said step of connecting the blanking electrodes connects said other of the pair of blanking electrodes of each aperture alternately to first and second potential lines along said first direction, said first potential line having a higher potential than said second potential line.
Claim 5
Dependent Claim
164 words
The method of producing the blanking aperture array as claimed in claim 1, wherein each aperture includes a pair of spaced, confronting sidewalls, and wherein said step of forming apertures includes the substeps of: forming a pair of grooves extending through said stacked epitaxial and impurity diffusion layers and reaching said semiconductor substrate, at positions respectively corresponding to and defining the corresponding portions of the confronting sidewalls of each aperture, by a trench etching step; forming an insulator layer on the surface of each of said pair of grooves; filling each of said pair of grooves with an electrode material, said electrode material being impurity doped polysilicon; removing the portions of said epitaxial layer and said impurity diffusion layer between each of said pair of grooves by an etching step; and completing the remaining portions of the sidewalls of each aperture, extending through the semiconductor substrate, by taper etching said semiconductor substrate in the direction from the bottom surface to the top surface thereof.
Claim 6
Dependent Claim
49 words
The method of producing the blanking aperture array as claimed in claim 4, wherein said substep of filling each of said pair of grooves with an electrode material is performed by a step of chemical vapor deposition of the impurity doped polysilicon into each of said pair of grooves.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |