Signal processing circuit

Claim 2

A signal processing circuit, comprising: means for storing instructions of arithmetic processes: means for decoding said instructions stored in said instruction storing means; means for storing data; means for carrying out a calculation of said data read from said data storing means in accordance with said instructions decoded by said decoding means; a multi-port type register circuit connected to said data storing means and said calculation means to store said read data and results of said arithmetic process temporally; said means for carrying out a calculation including at least two arithmetic logic units for carrying out arithmetic logic calculations of said data from said data storage means and a multiplying and accumulating circuit for carrying out multiplication and accumulation of said data from said data storage means, said at least two arithmetic logic units connected in parallel with said multi-port type register circuit; and means coupling said arithmetic logic units and said multiplying and accumulating circuit in parallel with said multi-port type register.

Claim 3

A signal processing circuit, according to claim 1, wherein: said at least two arithmetic logic units carry out different calculations by a common operated of said decoding means.

Claim 4

A signal processing circuit, comprising: means for storing instructions of arithmetic processes: means for decoding said instructions stored in said instruction storing means; means for storing data; means for carrying out a calculation of said data read from said data storing means in accordance with said instructions decoded by said decoding means; a multi-port type register circuit connected to said data storing means and said calculation means to store said read data and results of said arithmetic process temporarily; said means for carrying out a calculation including at least two arithmetic logic units for carrying out arithmetic logic calculations of said data read from said data storage means and a multiplying and accumulating circuit for carrying out multiplication and accumulation of said data from said data storage means, said at least two arithmetic logic units connected in parallel with said multi-port type register circuit; means coupling said arithmetic logic units and said multiplying and accumulating circuit in parallel with said multi-port type register; and a shift register circuit connected in parallel to said multi-port type register circuit and said arithmetic logic units and said multiplying and accumulating circuit.

Claim 5

A signal processing circuit, comprising: means for storing instructions of arithmetic processes: means for decoding said instructions stored in said instruction storing means; means for storing data; means for carrying out a calculation of said data read from said data storing means in accordance with said instructions decoded by said decoding means; a multi-port type register circuit connected to said data storing means and said calculation means to store said read data and results of said arithmetic process temporarily; said means for carrying out a calculation including at least two arithmetic logic units for carrying out arithmetic logic calculations of said data read from said data storage means and a multiplying and accumulating circuit for carrying out multiplication and accumulation of said data from said data storage means, said at least two arithmetic logic units connected in parallel with said multi-port type register circuit; means coupling said arithmetic logic units and said multiplying and accumulating circuit in parallel with said multi-port type register; and a shift register circuit connected in parallel to said multi-port type register circuit and said arithmetic logic units and said multiplying and accumulating circuit.

Claim 6

A signal processing circuit, comprising: a instruction memory for storing instructions of arithmetic processes; an instruction decoder for decoding said instructions read from said instruction memory, said instruction decoder including decode registers for storing decoded instruction; a data memory for storing data necessary for arithmetic processes; a multi-port type register circuit for storing data read from said data memory and results of said arithmetic processes; an address decoder for designating an address of said multi-port type register circuit by receiving said decoded instructions from said decode register; first and second arithmetic logic units for carrying out arithmetic logic calculation of said data and said results supplied from said multi-port type register circuit, said first and second arithmetic logic units being connected in parallel to said multi-port type register circuit; and a multiplying and accumulating circuit for carrying out multiplication and accumulation of said data and said results supplied from said multi-port type register circuit, said multiplying and accumulating circuit being connected in parallel with said first and second arithmetic logic units to said multi-port type register circuit.

Claim 7

A signal processing circuit, comprising: a instruction memory for storing instructions of arithmetic processes; an instruction decoder for decoding said instructions read from said instruction memory, said instruction decoder including decode registers for storing decoded instruction; a data memory for storing data necessary for arithmetic processes; a multi-port type register circuit for storing data read from said data memory and results of said arithmetic processes; an address decoder for designating an address of said multi-port type register circuit by receiving said decoded instructions from said decode register; first and second arithmetic logic units for carrying out arithmetic logic calculation of said data and said results supplied from said multi-port type register circuit, said first and second arithmetic logic units being connected in parallel to said multi-port type register circuit; and a multiplying and accumulating circuit for carrying out multiplication and accumulation of said data and said results supplied from said multi-port type register circuit, said multiplying and accumulating circuit being connected in parallel with said first and second arithmetic logic units to said multi-port type register circuit.