Semiconductor memory device

Claim 2

A semiconductor memory device, comprising: (a) a memory cell array formed by arranging a plurality of electrically rewritable non-volatile memory cells in matrix form, each memory cell including a memory MOS transistor with a floating gate, an erase transistor having a first terminal connected to a control gate of said memory MOS transistor so as to be selectively turned on, and a write transistor having a first terminal connected in series with said memory MOS transistor so as to be selectively turned on; (b) address lines connected in common to gates of said erase transistors belonging to the same address and connected to gates of said write transistors of said memory cells belonging to the same address; (c) erase lines provided for respective bits, said erase lines being connected to second terminals of said erase transistors belonging to the same bit; (d) write lines provided for respective bits, said write lines being connected to second terminals of said write transistors belonging to the same bit; and (e) control means for applying a high rewriting voltage to either one of said erase lines and said write lines belonging to a bit according to a bit logical value of an input data, in case of a rewrite operation for a bit, whereby an erase operation and a write operation can be performed simultaneously.

Claim 3

The semiconductor memory device of claim 1, wherein said control means comprises for each bit a first switch circuit for applying a rewriting voltage to either one of said write lines and said erase lines and a second switch circuit for applying a zero voltage to the other thereof, according to a bit logical value of input data and in response to a rewrite signal.

Claim 4

The semiconductor memory device of claim 2, which further comprises a data input/output circuit connected to said control means, for providing a given input data to a respective bit position of said control means reliably.

Claim 5

A semiconductor memory device, comprising: (a) A memory cell array formed by arranging a plurality of electrically rewritable non-volatile memory cells in matrix form, each memory cell including a memory MOS transistor with a floating gate, an erase transistor whose first terminal is connected to a control gate of said memory transistor so as to be selectively turned on, and a write transistor having a first terminal connected in series with said memory MOS transistor so as to be selectively turned on; (b) address lines connected in common to gates of said erase transistors belonging to the same address and connected to gates of said write transistors of said memory cells belonging to the same address; (c) erase lines provided for respective bits, said erase lines being connected to second terminals of said erase transistors belonging to the same bit; (d) write lines provided for respective bits, said write lines being connected to second terminals of said write transistors belonging to the same bit; (e) control means for applying a predetermined high voltage to either one of said erase lines and said write lines belonging to a bit according to a bit logical value of each selected bit of an input data, in the case of a read or a rewrite operation for a bit, whereby an erase operation and a write operation can be performed simultaneously.

Claim 6

A semiconductor memory device, comprising: (a) A memory cell array formed by arranging a plurality of electrically rewritable non-volatile memory cells in matrix form, each memory cell including a memory MOS transistor with a floating gate, an erase transistor whose first terminal is connected to a control gate of said memory transistor so as to be selectively turned on, and a write transistor having a first terminal connected in series with said memory MOS transistor so as to be selectively turned on; (b) address lines connected in common to gates of said erase transistors belonging to the same address and connected to gates of said write transistors of said memory cells belonging to the same address; (c) erase lines provided for respective bits, said erase lines being connected to second terminals of said erase transistors belonging to the same bit; (d) write lines provided for respective bits, said write lines being connected to second terminals of said write transistors belonging to the same bit; (e) control means for applying a predetermined high voltage to either one of said erase lines and said write lines belonging to a bit according to a bit logical value of each selected bit of an input data, in the case of a read or a rewrite operation for a bit, whereby an erase operation and a write operation can be performed simultaneously.

Claim 7

The semiconductor memory device according to claim 4, wherein said control means has means for applying a high rewriting voltage for data rewrite operation and means for applying a relatively high reading voltage for data read operation.

Claim 8

The semiconductor memory device of claim 4, wherein said control means comprises for each bit a first switch circuit for applying a rewriting voltage to either one of said write lines and said erase lines and a second switch circuit for applying a zero voltage to the other thereof, according to respective data value of a selected bit and in response to a rewrite signal.

Claim 9

The semiconductor memory device of claim 5, which further comprises a bit select input circuit connected to said control means, for providing a given input data to respective bit position of said control means reliably.