US5258632A
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Velocity modulation transistor
Assignee: Sanyo Electric Co Ltd
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Filing: 1991-08-14
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Granted: 1993-11-02
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Expires: 2011-08-14
Abstract
Abstract A velocity modulation transistor has a first barrier layer, first channel layer, second barrier layer, second channel layer, third barrier layer, input/output electrode that and control electrode are laminated on a semi-insulative substrate in this order, The electron affinity of the first channel layer is larger than that of the second channel layer. The energy difference between the first level and the second level can be obtained according to the difference in the electron affinity between the first and second channel layers as well as to the control of the film thickness of the first and second channel layers, whereby the velocity modulation effect at room temperature becomes large.
Inventors
- 👤 Minoru Sawada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/204
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
204 words
A velocity modulation transistor, comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer wherein said first channel layer is an InGaAs layer; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer comprising n-type GaAs formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; and a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer.
Claim 2
Dependent Claim
204 words
A velocity modulation transistor, comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer wherein said first channel layer is an InGaAs layer; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer comprising n-type GaAs formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; and a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer.
Claim 3
Dependent Claim
210 words
A velocity modulation transistor comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer; and said first channel layer being an InGaAs layer and said second channel layer being an n-type InGaAlAs layer.
Claim 4
Dependent Claim
210 words
A velocity modulation transistor comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer; and said first channel layer being an InGaAs layer and said second channel layer being an n-type InGaAlAs layer.
Claim 5
Dependent Claim
203 words
A velocity modulation transistor comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer; a first channel layer formed on said first barrier layer wherein said first channel layer is an InGaAs layer; a second barrier layer formed on said first channel layer; a second channel layer comprising n-type InGaAlAs formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer; and said first barrier being an n-type InAlAs layer, said second barrier layer being an InAlAs layer, and said third barrier layer being an n-type InAlAs layer.
Claim 6
Dependent Claim
203 words
A velocity modulation transistor comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer; a first channel layer formed on said first barrier layer wherein said first channel layer is an InGaAs layer; a second barrier layer formed on said first channel layer; a second channel layer comprising n-type InGaAlAs formed on said second barrier layer, wherein a film thickness of said first channel layer is larger than a film thickness of said second channel layer, and a band gap of said first channel layer is smaller than a band gap of said second channel layer; a third barrier layer formed on said second channel layer; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer; and said first barrier being an n-type InAlAs layer, said second barrier layer being an InAlAs layer, and said third barrier layer being an n-type InAlAs layer.
Claim 7
Dependent Claim
181 words
A velocity modulation transistor, comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer wherein said first channel layer is a superlattice film layer in which a plurality of InGaAs layers and GaAs layers are laminated and alternately interleaved therein; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer comprising n-type GaAs formed on said second barrier layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; and a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer.
Claim 8
Dependent Claim
181 words
A velocity modulation transistor, comprising: a semi-insulative substrate; a semiconductor layer formed on said semi-insulative substrate; a first barrier layer formed on said semiconductor layer wherein said first barrier layer is an n-type AlGaAs layer; a first channel layer formed on said first barrier layer wherein said first channel layer is a superlattice film layer in which a plurality of InGaAs layers and GaAs layers are laminated and alternately interleaved therein; a second barrier layer formed on said first channel layer wherein said second barrier layer is an AlGaAs layer; a second channel layer comprising n-type GaAs formed on said second barrier layer; a third barrier layer formed on said second channel layer wherein said third barrier layer is n-type AlGaAs; a third semiconductor layer partially formed on said third barrier layer whereon an input and an output electrode are formed; and a control electrode formed on a surface area of said third barrier layer where said third semiconductor layer is not present, wherein the electron affinity of said first channel layer is larger than that of said second channel layer.
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