Instruction cache buffer with program-flow control

Claim 2

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; a direct program instruction path; means for writing program instructions from said external memory selectively to one of said cache memory, said first-in-first-out memory, and said direct program instruction path, in response to a first control signal; means for reading said program instructions selectively from one of said cache memory, said first-in-first-out memory, and said direct program instruction path, to said processor in response to a second control signal; and control means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched and based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instructions being transferred for selecting a processor program instruction buffering path for a particular processor program by dynamically generating said first and second control signals, said first control signal having first characteristics that depend on said program instructions, said second control signal having second characteristics that depend on said program instructions, said first and said second characteristics indicating to said means for writing and said means for reading respectively, which one of said cache memory, said first-in-first-out memory, or said direct program instruction path is selected.

Claim 3

An intelligent program-flow controlled memory buffer in accordance with claim 1, further comprising means for flushing said cache memory and said first-in-first-out memory in response to predetermined conditions of each of said indicia.

Claim 4

An intelligent program-flow controlled memory buffer in accordance with claim 1, wherein said cache memory is a dual ported cache memory, said dual ports providing concurrent coupling of said cache memory to said means for reading and said means for writing.

Claim 5

An intelligent program-flow controlled memory buffer in accordance with claim 1, wherein said indicia comprises instruction type received from said external memory, instruction type requested by said processor, range of addresses stored in said cache memory, contents of said cache memory, and contents of said first-in-first-out memory.

Claim 6

An intelligent program-flow controlled memory buffer in accordance with claim 4, wherein said control means comprises a means for sensing the type of program instruction, the range of the addresses stored in the cache memory and the contents of said cache memory and said first-in-first-out memory.

Claim 7

An intelligent program-flow controlled memory buffer in accordance with claim 1, wherein said intelligent program-flow controlled memory buffer is implemented utilizing very large scale integrated circuit techniques in a single integrated circuit chip.

Claim 8

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instruction data from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; and control means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data and based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data being transferred for selecting a processor program instruction data path for a particular processor program by dynamically generating said first and second control signals, said first control signal having first characteristics that depend on said program instruction data, said second control signal having second characteristics that depend on said program instruction data, said first and said second characteristics indicating to said means for writing and said means for reading respectively, which one of said cache memory or said first-in-first-out memory is selected.

Claim 9

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instruction data from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; and control means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data and based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data being transferred for selecting a processor program instruction data path for a particular processor program by dynamically generating said first and second control signals, said first control signal having first characteristics that depend on said program instruction data, said second control signal having second characteristics that depend on said program instruction data, said first and said second characteristics indicating to said means for writing and said means for reading respectively, which one of said cache memory or said first-in-first-out memory is selected.

Claim 10

An intelligent program-flow controlled memory buffer in accordance with claim 7, further comprising means for flushing said cache memory and said first-in-first-out memory in response to predetermined conditions of each of said indicia.

Claim 11

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instructions from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instructions selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; and control means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched and said condition of each of said predetermined plurality of indicia of said program instructions being transferred for selecting a processor program instruction buffering path for a particular processor program by dynamically generating said first and second control signals, said first control signal having first characteristics that depend on said program instructions, said second control signal having second characteristics that depend on said program instructions, said first and said second characteristics indicating to said means for writing and said means for reading respectively, which one of said cache memory or said first-in-first-out memory is selected.

Claim 12

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instructions from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instructions selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; and control means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched and said condition of each of said predetermined plurality of indicia of said program instructions being transferred for selecting a processor program instruction buffering path for a particular processor program by dynamically generating said first and second control signals, said first control signal having first characteristics that depend on said program instructions, said second control signal having second characteristics that depend on said program instructions, said first and said second characteristics indicating to said means for writing and said means for reading respectively, which one of said cache memory or said first-in-first-out memory is selected.

Claim 13

An intelligent program-flow controlled memory buffer in accordance with claim 7, wherein said indicia comprises instruction type received from said external memory, instruction type requested by said processor, range of addresses stored in said cache memory, contents of said cache memory, and contents of said first-in-first-out memory.

Claim 14

An intelligent program-flow controlled memory buffer in accordance with claim 10, wherein said control means comprises a means for sensing the type of program instruction, the range of the addresses stored in the cache memory and the contents of said cache memory and said first-in-first-out memory.

Claim 15

An intelligent program-flow controlled memory buffer in accordance with claim 7, wherein said intelligent program-flow controlled memory buffer is implemented utilizing very large scale integrated circuit techniques in a single integrated circuit chip.

Claim 16

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; a direct program instruction data path; means for writing program instruction data from said external memory selectively to one of said cache memory, said first-in-first-out memory, and said direct data path, in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory, said first-in-first-out memory, and said direct data path, to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data; means for selecting a processor program instruction data path for a particular processor program instruction retrieval from among a plurality of available data paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined data paths comprising said cache memory, said first-in-first-out memory, and said direct data path, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory, said first-in-first-out memory, or said direct data path.

Claim 17

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; a direct program instruction data path; means for writing program instruction data from said external memory selectively to one of said cache memory, said first-in-first-out memory, and said direct data path, in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory, said first-in-first-out memory, and said direct data path, to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data; means for selecting a processor program instruction data path for a particular processor program instruction retrieval from among a plurality of available data paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined data paths comprising said cache memory, said first-in-first-out memory, and said direct data path, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory, said first-in-first-out memory, or said direct data path.

Claim 18

An intelligent program-flow controlled memory buffer in accordance with claim 13, further comprising means for flushing said cache memory and said first-in-first-out memory in response to predetermined conditions of each of said indicia.

Claim 19

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow sped memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; a direct program instruction path; means for writing program instructions from said external memory selectively to one of said cache memory, said first-in-first-out memory, and said direct program instruction path in response to a first control signal; means for reading said program instructions selectively from one of said cache memory, said first-in-first-out memory, and said direct program instruction path, to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched; means for selecting a processor program instruction buffering path for a particular processor program instruction retrieval from among a plurality of available program instruction paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instructions, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined program instruction paths comprising said cache memory, said first-in-first-out memory, and said direct program instruction path, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory, said first-in-first-out memory, or said direct program instruction path.

Claim 20

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow sped memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; a direct program instruction path; means for writing program instructions from said external memory selectively to one of said cache memory, said first-in-first-out memory, and said direct program instruction path in response to a first control signal; means for reading said program instructions selectively from one of said cache memory, said first-in-first-out memory, and said direct program instruction path, to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched; means for selecting a processor program instruction buffering path for a particular processor program instruction retrieval from among a plurality of available program instruction paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instructions, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined program instruction paths comprising said cache memory, said first-in-first-out memory, and said direct program instruction path, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory, said first-in-first-out memory, or said direct program instruction path.

Claim 21

An intelligent program-flow controlled memory buffer in accordance with claim 13, wherein said indicia comprises instruction type received from said external memory, instruction type requested by said processor, range of addresses stored in said cache memory, contents of said cache memory, and contents of said first-in-first-out memory.

Claim 22

An intelligent program-flow controlled memory buffer in accordance with claim 13, wherein said intelligent program-flow controlled memory buffer is implemented utilizing very large scale integrated circuit techniques in a single integrated circuit chip.

Claim 23

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instruction data from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data; means for selecting a processor program instruction data path for a particular processor program instruction retrieval from among a plurality of available data paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined data paths comprising said cache memory and said first-in-first-out memory, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory or said first-in-first-out memory.

Claim 24

An intelligent program-flow controlled memory buffer for buffering program instruction data from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instruction data from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instruction data selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instruction data; means for selecting a processor program instruction data path for a particular processor program instruction retrieval from among a plurality of available data paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instruction data, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined data paths comprising said cache memory and said first-in-first-out memory, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory or said first-in-first-out memory.

Claim 25

An intelligent program-flow controlled memory buffer in accordance with claim 18, further comprising means for flushing said cache memory and said first-in-first-out memory in response to predetermined conditions of each of said indicia.

Claim 26

An intelligent program-flow controlled memory buffer in accordance with claim 18, wherein said cache memory is a dual ported cache memory, said dual ports providing concurrent coupling of said cache memory to said means for reading and said means for writing.

Claim 27

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instructions from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instructions selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched; means for selecting a processor program instruction buffering path for a particular processor program instruction retrieval from among a plurality of available program instruction paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instructions, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined program instruction paths comprising said cache memory and said first-in-first-out memory, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information d determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory or said first-in-first-out memory.

Claim 28

An intelligent program-flow controlled memory buffer for buffering program instructions from an external memory made up of relatively slow speed memory elements to a processor which operates at relatively high speeds, said program-flow controlled memory buffer comprising: at least one cache memory made up of relatively high speed memory elements; at least one first-in-first-out memory made of relatively high speed memory elements, said first-in-first-out memory being substantially smaller than said cache memory; means for writing program instructions from said external memory selectively to one of said cache memory and said first-in-first-out memory in response to a first control signal; means for reading said program instructions selectively from one of said cache memory and said first-in-first-out memory to said processor in response to a second control signal; means for sensing a condition of each of a predetermined plurality of indicia of said program instructions to determine what type of instruction is currently being prefetched; means for selecting a processor program instruction buffering path for a particular processor program instruction retrieval from among a plurality of available program instruction paths based on predetermined rules and said condition of each of said predetermined plurality of indicia of said program instructions, so that efficient processor operation is achieved for different types of program instructions, said plurality of predefined program instruction paths comprising said cache memory and said first-in-first-out memory, said types of program instruction comprising repetitive program loops, non-repetitive instruction sequences, conditional jumps, and conditional branches; and means for generating said first and second control signals having control information d determined by said means for selecting, said control information comprising information to which said means for writing and said means for reading are responsive to, and which identifies one of said cache memory or said first-in-first-out memory.

Claim 29

An intelligent program-flow controlled memory buffer in accordance with claim 18, wherein said intelligent program-flow controlled memory buffer is implemented utilizing very large scale integrated circuit techniques in a single integrated circuit chip.