Cache memory control circuit

Claim 2

A cache memory control circuit comprising: second memory means (26) having a smaller capacity than first memory means and operating at a faster speed than said first memory means; instruction control means (10) for executing instructions read from said first memory means, said instruction control means (10) containing an instruction register (11) to set an instruction which should be executed by said instruction control means (10); generator means (15) which is controlled by said instruction control means (10) and generates an address to write onto said first memory means an operand designated by an instruction set to said instruction register (11); determining means (14) which detects a predetermined bit of instruction set to said instruction register (11) and determines whether operand designated by said instruction is to be written onto said second memory means (26); and means which writes said operand and an address generated from said generator means (15) onto said second memory means (26) when said determining means (14) has determined that the operand designated by said instruction is to be written onto said second memory means (26).

Claim 3

The circuit of claim 1, wherein said writing means contains means which writes said operand and address onto said second memory means (26) and writes said operand onto the position of said address of said first memory means.

Claim 4

The circuit of claim 1 or 2, wherein said generator means includes a plurality of address registers (15) that are selectively designated by instructions, and means (12) for calculating the address of said first memory means based upon the content of the selected address register.

Claim 5

The circuit of claim 3, wherein said determining means (14) includes means which decides to write the operand designated by said instruction onto said second memory means (26) when said instruction designates a first address register among said plurality of address registers (15), and the content of said first address register is renewed every time after said operand is written onto said first and second memory means.

Claim 6

A memory control circuit comprising: second memory means (26) having a smaller capacity than first memory means and operating at a faster speed than said first memory means; instruction control means (10) for executing instructions read from said first memory means, said instruction control means (10) containing an instruction register (11) to set an instruction which should be executed by said instruction operation means (10); generator r.eans (15) which is controlled by said instruction control means (10) and generates an address to read from said first memory means an operand designated by an instruction set to said instruction register (11); determining means (14) which determines whether or not a predetermined bit of instruction set to said instruction register (11) satisfies a predetermined condition; and first means which, when the result determined by said determining means (14) is affirmative, detects whether the address generated by said generator means (15) exists in said second memory means (26), which, when said address exists therein, reads out an operand that is stored in the same position as the position storing said address, which, when said address is not stored, produces a reading request to said first memory means to read an operand at said address position of said first memory means, and which, when the result determined by said determining means (14) is negative, immediately sends a read request to said first memory means to read an operand at said address position of said first memory means; wherein said instruction control means (10) controls to execute said instruction relying upon the operand read from said first or second memory means.

Claim 7

A memory control circuit comprising: second memory means (26) having a smaller capacity than first memory means and operating at a faster speed than said first memory means; instruction control means (10) for executing instructions read from said first memory means, said instruction control means (10) containing an instruction register (11) to set an instruction which should be executed by said instruction operation means (10); generator r.eans (15) which is controlled by said instruction control means (10) and generates an address to read from said first memory means an operand designated by an instruction set to said instruction register (11); determining means (14) which determines whether or not a predetermined bit of instruction set to said instruction register (11) satisfies a predetermined condition; and first means which, when the result determined by said determining means (14) is affirmative, detects whether the address generated by said generator means (15) exists in said second memory means (26), which, when said address exists therein, reads out an operand that is stored in the same position as the position storing said address, which, when said address is not stored, produces a reading request to said first memory means to read an operand at said address position of said first memory means, and which, when the result determined by said determining means (14) is negative, immediately sends a read request to said first memory means to read an operand at said address position of said first memory means; wherein said instruction control means (10) controls to execute said instruction relying upon the operand read from said first or second memory means.

Claim 8

The circuit of claim 5, wherein said second memory means (26) stores the address and the operand in relation to each other, and whether the address generated by said generator means has already been stored therein is referenced by said first means.

Claim 9

The circuit of claim 5 or 6, wherein said generator means includes a plurality of address registers (15) that will be selectively designated by an instruction and means (12) for calculating an address of said first memory means relying upon the content of the selected address register.

Claim 10

The circuit of claim 7, wherein said determining means (14) includes means which decides to reference whether or not the address of operand designated by said instruction exists in said second memory means (26) when said instruction designates the first address register among said plurality of address registers (15), and the content of said first address register is renewed every time when said operand is read out from said first memory means or from said second memory means (26).

Claim 11

The circuit of any of claims 1 to 8, wherein said cache memory control circuit is formed on a single chip.

Claim 12

A cache memory control circuit comprising: a cache memory (26) onto which will be copied part of the content of a memory; data processing means for processing instruction read from said memory; means (14) which determines whether the access operation for said memory is directed to a particular region or not; and means which, when the access operation is directed to said particular region, causes said cache memory (26) to hold at least the data that will be accessed in response to the output of said determining means (14), and which, when the access operation for reading data is operated to a region other than said particular region, permits the access operation to be executed irrespective of the cache memory (26).

Claim 13

A cache memory control circuit comprising: a cache memory (26) onto which will be copied part of the content of a memory; data processing means for processing instruction read from said memory; means (14) which determines whether the access operation for said memory is directed to a particular region or not; and means which, when the access operation is directed to said particular region, causes said cache memory (26) to hold at least the data that will be accessed in response to the output of said determining means (14), and which, when the access operation for reading data is operated to a region other than said particular region, permits the access operation to be executed irrespective of the cache memory (26).

Claim 14

The circuit of claim 10, wherein said particular region is assigned to the stack.