Fifo memory with decreased fall-through delay

Claim 2

A first in, first out data memory (10) comprising a plurality of sequentially coupled memory stages (50), each having input means (52) for writing data; output means coupled to the last of said stages for reading data from said data memory; means (48) for shifting data written to any one of said memory stages sequentially through said memory stages to the last of said memory stages which does not presently contain data; and means (40) for selectively writing data directly into the memory stage nearest the output means (42) which does not presently contain data for the purpose of decreasing fall-through delay time.

Claim 3

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (28 - 36) and coupled for cascade operation; input means (52) coupled to each section for writing data thereto; output means (42) coupled to the last of said sections for reading data from said data memory; means (48) for shifting data written to any one of said stages sequentially through the stages to the last of the stages which does not presently contain data; and means (40) for selectively writing data directly into the section nearest the output means which is not presently full of data for the purpose of decreasing fall through delay time.

Claim 4

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (28 - 36) and coupled for cascade operation; input means (52) coupled to each section for writing data thereto; output means (42) coupled to the last of said sections for reading data from said data memory; means (48) for shifting data written to any one of said stages sequentially through the stages to the last of the stages which does not presently contain data; and means (40) for selectively writing data directly into the section nearest the output means which is not presently full of data for the purpose of decreasing fall through delay time.

Claim 5

A first in, first out data memory (10) as claimed in claim 2, wherein each of said sections (28 - 36) has a smaller number of register stages (50) than the one preceding it.

Claim 6

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (26 - 28) and coupled for cascade operation; input means (52) coupled to each section for writing data thereto; a bypass bus (40), selectively coupled to the input means of each section, through which data is introduced; output means (42), coupled to the last of said sections, for reading data from said data memory; first status means (48), associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means (48), associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means (48), coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means (48), coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 7

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (26 - 28) and coupled for cascade operation; input means (52) coupled to each section for writing data thereto; a bypass bus (40), selectively coupled to the input means of each section, through which data is introduced; output means (42), coupled to the last of said sections, for reading data from said data memory; first status means (48), associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means (48), associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means (48), coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means (48), coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 8

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (28 - 36) and coupled for cascade operation; each section having a smaller number of register stages than the one preceding it; input means (52) coupled to each section for writing data thereto; a bypass bus (40), selectively coupled to the input means of each section, through which data is introduced; output means (42), coupled to the last of said sections, for reading data from said data memory; first status means (48), associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means (48), associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means (48), coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means (48), coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 9

A first in, first out data memory (10) comprising a plurality of shift register stages (50), sequentially arranged in sections (28 - 36) and coupled for cascade operation; each section having a smaller number of register stages than the one preceding it; input means (52) coupled to each section for writing data thereto; a bypass bus (40), selectively coupled to the input means of each section, through which data is introduced; output means (42), coupled to the last of said sections, for reading data from said data memory; first status means (48), associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage; first control logic means (48), associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage; second status means (48), coupled to each of said sections, for indicating either a full or not full data condition for that section; and second control logic means (48), coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus; whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

Claim 10

A first in, first out data memory (10) as claimed in claim 5, further including first clock input means (68), coupled to said bypass bus, for controlling the rate at which data is introduced onto said bypass bus; and second clock input means (80), coupled to said output means, for controlling the rate at which data is read from said data memory.

Claim 11

A first in, first out data memory (10) as claimed in claim 4, wherein the number of register stages (50) in the last of said sections (28 - 36) is governed by the relationship and the number of register stages in preceding sections is governed by the relationship to optimize said register section lengths so that a continuous input data stream will not have time delay gaps introduced therein upon reading from said output means.

Claim 12

A first in, first out data memory (10) as claimed in claim 5, wherein said memory is constructed as a solid-state integrated circuit.